Ferroelectric, Analog Resistive Switching in Back‐End‐of‐Line Compatible TiN/HfZrO4/TiOx Junctions

Due to their compatibility with complementary metal–oxide–semiconductor technologies, hafnium‐based ferroelectric devices receive increasing interest for the fabrication of neuromorphic hardware. Herein, an analog resistive memory device is fabricated with a process developed for back‐end‐of‐line integration. A 4.5 nm‐thick HfZrO4 (HZO) layer is crystallized into the ferroelectric phase, a thickness thin enough to allow electrical conduction through the layer. A TiOx interlayer is used to create an asymmetric junction as required for transferring a polarization state change into a modification of the conductivity. Memristive functionality is obtained, both in the pristine state and after ferroelectric wake‐up, involving redistribution of oxygen vacancies in the ferroelectric layer. The resistive switching is shown to originate directly from the ferroelectric properties of the HZO layer.

Mimicking the brain, "deep-learning" algorithms are structured into layers of interconnected neurons. As the information flows from one layer to the next, matrix-vector multiplications are performed. The matrix elements, called "synaptic weights" by analogy with the biological synapses, are updated during the training of the neural network. With current "classical" computer architectures, vector-matrix multiplications demand a large computing power. To keep pace with the ever increasing workload and neural network complexity, efficient bioinspired hardware accelerators supporting deep-learning are being developed. [1,2] Their building block, emulating the synapse, is the memristor: [3] a resistance whose value can vary reversibly upon an external stimuli, in a persistent way. The matrix-vector multiplication is then performed by applying input potentials on a crossbar array of memristors, and measuring the output currents. [4] Among the technologies explored to demonstrate memristors, [5,6] the choice of ferroelectric materials is attractive as the polarization can be changed by the application of an external electric field and is remnant: the nondestructive readout of the synapse is possible for bias fields across the ferroelectric layer lower than its coercive field. The growth of high-quality epitaxial thin films allowed the demonstration of two and three terminals ferroelectric memristors: ferroelectric tunnel junctions (FTJs) with perovskites [7][8][9][10] as well as recently with Hf ZrO 4 (HZO), [11] ferroelectric field-effect transistors (FeFETs). [12] However, integrating such synapses on complementary metal-oxide-semiconductor (CMOS) neurons remains challenging and expensive, requiring flip chip or waferbonding techniques. Recently, the discovery of ferroelectricity in doped hafnium oxide, [13] in particular HZO [14] enabled the demonstration of ferroelectric memristors in the front-end-of-line (FEOL), [15][16][17] and transistors with back-end-of-line (BEOL) compatible processes. [18,19] The latter is made possible by annealing, permitting a crystallization in the ferroelectric phase with a low thermal budget. [20] BEOL processes not exceeding 400 C is critical for industrializing beyond-von-Neumann hardware in CMOS-based silicon technology. A two-terminal ferroelectric memristor consists of a ferroelectric layer separating two different electrodes. Upon polarization reversal, the energy profile and thus the transport probability of carriers across the ferroelectric layer is modified. Their fabrication is challenging as the ferroelectric layer must be thick enough to stabilize ferroelectricity, a fortiori in multiple configurations, but thin enough to allow electric conduction. These conditions have been obtained for polycrystalline HZO at temperatures above 450 C. [21][22][23][24][25] A reduced thermal budget is less critical for thicker films: 10 nm layers have been, for example, crystallized at 400 C. [26][27][28] In this article, we demonstrate nonvolatile resistive switching (memristive functionality) in a 4.5 nm-thick ferroelectric layer in a BEOL compatible stack. A reduced thermal budget (%375 C) is used as well as abundant and CMOS compatible materials (Hf, Zr, and Ti). We show that resistive switching is enhanced after ferroelectric wake-up and that it originates from the ferroelectric polarization.
The cointegration of ferroelectric memristive synapses in the BEOL with CMOS neurons is challenging because the thermal budget should not exceed 400 C to avoid any damage to the FEOL circuitry. The choice of materials-TiN, HZO, and an interlayer of conducting TiO x -is motivated by the moderate temperature of the atomic layer deposition (ALD) growth process, as well as the conformal growth mode enabling eventual 3D integration. First, a 20 nm-thick bottom electrode of TiN is deposited on a SiO 2 //Si substrate. Then, a 3.5 nm-thick TiO x interlayer is deposited to create an asymmetry in the energy profile of the oxide barrier, necessary for resistive switching upon ferroelectric Due to their compatibility with complementary metal-oxide-semiconductor technologies, hafnium-based ferroelectric devices receive increasing interest for the fabrication of neuromorphic hardware. Herein, an analog resistive memory device is fabricated with a process developed for back-end-of-line integration. A 4.5 nm-thick Hf ZrO 4 (HZO) layer is crystallized into the ferroelectric phase, a thickness thin enough to allow electrical conduction through the layer. A TiO x interlayer is used to create an asymmetric junction as required for transferring a polarization state change into a modification of the conductivity. Memristive functionality is obtained, both in the pristine state and after ferroelectric wake-up, involving redistribution of oxygen vacancies in the ferroelectric layer. The resistive switching is shown to originate directly from the ferroelectric properties of the HZO layer. polarization reversal. [23] On top is a 4.5 nm-thick HZO layer and a 10 nm-thick TiN top electrode. All the above layers are amorphous after the ALD deposition. The choice of TiN as a capping layer is to promote the crystallization of HZO in the ferroelectric phase by a mechanical constraint during the annealing. [29] The crystallization at a moderate thermal budget is obtained using a millisecond flash lamp anneal (ms-FLA) [20] where the wafer is preheated to 375 C, then exposed to a 20 ms long flash of 70 J cm À2 . The I d -V g characteristics of p-and n-channel metal-oxide-semiconductor (130 nm) test transistors were not affected by such treatment, showing the CMOS compatibility of the process. The grazing incidence X-ray diffraction (GIXRD) spectrum in Figure 1 shows HZO crystallized in the orthorhombic or tetragonal phase and that no fraction of monoclinic phase is found. The Scherrer fit of the HZO peak at 30 indicates that the in-plane grain size is 3.5-4.5 nm, for a k factor of 0.7-1.
X-ray reflectivity (XRR) spectra indicate sharp interfaces with small roughness ( Figure S1, Supporting Information). After deposition of a top W electrode, circular capacitors are then fabricated using standard optical lithography techniques described in the Experimental Section. The diameter is chosen in the range 40-140 μm to enable the measurement of the resistance for voltages smaller than the coercive field of the 4.5 nm-thick HZO, i.e., in the 10 À3 -10 À2 V range. With this constraint, the footprint of the devices can in principle be reduced by thinning the HZO layer: ferroelectricity was demonstrated in HZO films (here, epitaxial) as thin as 2 nm. [30,31] To demonstrate memristive functionality of the resistive memory, we first apply "write" DC pulses of a voltage V write across the device, whereas the bottom electrode (HZO/TiO x / TiN interface) is grounded. The bias is then set back to zero, and %10 s later , the resistance of the junction is measured by applying a "read" voltage of only 100 mV to the top electrode. The value of 100 mV is chosen to remain below the coercive field of the ferroelectric, thus not modifying the state of the device (nondestructive readout). The results of this write/read experiment for three different devices of same dimensions (variability %6%) are shown in Figure 2.
After applying V write ¼ À1.5 V, the junction is in a low resistive state (LRS). Upon the application of pulses of increasing voltage, the resistance remains stable until it increases sharply at The resistance then gradually increases (RESET), and the device reaches a high resistive state (HRS). With pulses of decreasing voltage, the resistance remains stable until it decreases sharply at V write ¼ À0.45 V. A gradual decrease in resistance is then observed until it reaches its initial value (LRS, SET). In the conditions of the experiment, a moderate drift of the LRS is observed (a few tens of kiloohms from cycle to cycle). A drift is also observed on a longer timescale: three devices poled in the LRS, HRS, and in an intermediate state, all see their resistance increase by 0.5 GOhms after 6 days (see Figure S2, Supporting Information). The memory of the state (LRS, HRS, or intermediate) is preserved. The experiment demonstrates the nonvolatile, analog, reversible resistive switching in the 4.5 nm-thick HZO device.
To get further insights on the mechanisms of conduction through the diode, the capacitors of various sizes (40-140 μm) were measured. The resistances in the LRS and HRS scale with the inverse of the area of the junction (see Figure S3, Supporting Information) indicating that the conduction is homogeneous and not due to the formation of a filament [32] through the HZO.  www.advancedsciencenews.com www.pss-rapid.com The ON/OFF ratio, defined as the ratio of the resistances in the HRS and the LRS, does not vary with the dimension of the devices, indicating that no pinning occurs at the edges and further pointing to a homogeneous conduction through the whole area of the device. In addition, similar devices with amorphous HZO were measured, and did not show resistive switching, as shown in Figure S4, Supporting Information. Figure S5, Supporting Information, shows the I-V characteristics for a pristine device and for a device after a "wake-up" of 10 5 cycles at þ/À2 V, 100 kHz: the shape of the characteristics at small bias is similar before and after wake-up, as well as in the HRS and the LRS, but the current is proportionally larger in the LRS and after wake-up. The I-V characteristics around V read ¼ 100 mV can be well described by a direct tunneling current (Brinkman model [33] ) through a symmetric barrier height of 0.42-0.48 eV. However, temperature-dependent measurements show that the current increases with the temperature, indicating that direct tunneling is not the dominant mechanism. For comparison, direct tunneling was observed at low temperature (50 K) in magnetic tunnel junctions on 2 nm-thick epitaxial HZO films. [30] Around 300 K and at small bias (V < 50 mV), Ohmic conduction is dominant (see Figure S6, Supporting Information) and is observed in a conduction band at 0.24 eV above the Fermi level in the LRS and 0.26 eV in the HRS: this difference of energy explains the resistive switching observed for V < 50 mV but also at V read (see Figure S5, Supporting Information). This value of energy difference between the conduction band and the Fermi level is small compared to the bandgap of HZO (%3.5 eV) which indicates the presence of an impurity level in the bandgap, from which the electrons are excited. [34] The change in the energy barrier between the LRS and the HRS is less than what is measured in epitaxial films of the same thickness, [35] which can be explained by the smaller effective polarization in polycrystalline films and the presence of defects at the interfaces of the ferroelectric film, screening the ferroelectric field-effect.
In thicker (10 nm) films, the read voltage is generally higher to obtain a measurable current, and the conduction mechanisms are different: in the study by Yoong et al., [36] the conduction around V read ¼ 2 V is described with thermionic injection, with a change in the barrier height as high as 0.1 eV. In junctions based on a dielectric interlayer [25,37] (e.g., Al 2 O 3 ), the energy profile is engineered in such a way that the electrons see the full width of the 10 nm HfO 2 film in the HRS and only the interlayer in the LRS, resulting in a large ON/OFF but in small current densities in the HRS: typically 10 À7 A cm À2 at a read voltage of 2 V, [17] compared to 10 À6 A cm À2 at a read voltage of 100 mV for the devices presented in this work. Figure 3 shows dynamic hysteresis measurements (DHMs) of an 80 μm diameter device during wake-up. The polarization of the pristine loop (in pink, thick line) is pinched and the remnant polarization is 2P r ¼ 7.5 μC cm À2 . After 1E5 cycles, the polarization increases to 2P r ¼ 24.6 μC cm À2 . The wake-up effect is known for HZO films and is attributed to the redistribution of oxygen vacancies. [38,39] From the current loops (thin lines), we observe that for the pristine device, the switching current is maximal at À1.6 and 1.8 V. These values then reduce to À0.7 and 0.7 V. This effect is explained by a strong ferroelectric domain pinning due to interfacial defects, [40] released by cycling the device at bias larger than the coercive field after wake-up. Similarly, smaller voltages are needed to switch the device from the HRS to the LRS, indicating that the electroresistance originates from the ferroelectricity, as further discussed later. Fatigue measurements (see Figure S7, Supporting Information) at an amplitude of 2 V and a frequency of 100 kHz show a maximal polarization after 5E6 cycles and a rupture after 2E8 cycles.
The experiment described earlier is repeated on an 80 μm diameter device after wake-up. The resistance measured at 100 mV for varying V write bias before and after the wake-up is shown in Figure 4.
The logarithmic scale emphasizes the increased ON/OFF ratio after wake-up, from 1.3 to 2.0. We have already established the  www.advancedsciencenews.com www.pss-rapid.com existence of an impurity level in the gap of HZO, which could be due to oxygen vacancies. [41] In this scenario, the decrease in the resistance in the LRS by a factor 5 can be a consequence of the redistribution of oxygen vacancies during wake-up from the interface to the bulk of the HZO layer. [39] For negative voltages, the saturation is reached at -1.0 V, compared to -1.4 V before wake-up, indicating a more efficient screening of the polarization in the LRS, as further discussed later. Figure 5 shows positive up negative down (PUND) measurements on the woken-up devices: the ranges within which resistive switching is observed correspond to the switching current (yellow regions in the inset showing the current as a function of the voltage: [À1.2;À0.2 V] and [0.1;1.6 V]), confirming the ferroelectric origin of the resistive switching.
The I-V characteristics of an 80 μm diameter device with and without wake-up are shown in Figure S5 in the Supporting Information. The inset shows the I-V characteristics at small fields in the HRSs and the LRSs, reflecting the measurements shown in Figure 2 and 4.
The I-V characteristics are highly nonlinear, which is of technological interest for neuromorphic computing: in selector-less crossbar arrays, nonlinear characteristics can prevent current sneak paths by blocking unselected devices. [42] In comparison, the I-V characteristics of a TiN/HZO (3 nm)/TiO x (3 nm)/TiN/ SiO 2 //Si device are quasilinear (not shown) and the current density is two orders of magnitude higher: this indicates that the TiO x /TiN contact is ohmic and that the resistance of the junction is dominated by the transport through the HZO layer. Ferroelectric diodes with metallic electrodes typically show p-n behavior for one polarization direction and n-p behavior for the opposite polarization direction. [27,43] In this article, before wake-up, the I-V characteristics are almost symmetric. After wake-up, the I-V characteristics keep the same polarity regardless of the polarization direction, showing that the energy band diagram of the TiN/HZO/TiO x junction is not structurally modified upon polarization reversal.
The proposed mechanism is shown in Figure 6 and is as follows: during the application of V write ¼ -1,5 V, the ferroelectric layer is polarized toward the TiO x layer (i). The polarization remains after setting V write to zero. In the TiN (metallic) layer, the polarization is screened across a distance of less than one angstrom. However, the carrier density in the TiO x layer is lower, and consequently, the screening occurs over a larger distance. [44] Oxygen deficient TiO x is a n-type semiconductor. [45] When the ferroelectric layer is polarized toward the TiO x layer, electrons screen the ferroelectric polarization and accumulate in the TiO x layer, which therefore becomes more conducting (LRS). Applying further pulses in the range from À1.35 to 0.1 V does not modify the resistance (no cumulative switching), consistent with an unchanged ferroelectric domain configuration. The HZO film is polycrystalline: above V write ¼ 0.1 V, a fraction of domains sees their polarization reverse for each additional pulse of increasing V write (ii). The broad distribution of coercive fields is due to the polycrystalline nature of the film and the size of the device that is large compared to the size of the HZO grains (see Figure 1). Reducing the lateral dimensions of the devices to several nanometers would typically lead to a discretization of the available intermediate states, as observed in nanoscale FeFETs. [16] Note that in epitaxial FTJs (in the absence of crystalline grains), analog resistive switching is also observable, with the gradual switching of nanometric ferroelectric domains. [46,47] The distribution appears broader when a positive bias is applied (ii) than when a negative bias is applied (iv): as the ferroelectric domains are polarized outward the TiO x layer, the latter is locally depleted in electrons and the polarization is not well screened. Consequently, some of the domains do not switch or switch back to the initial direction, until sufficient surrounding domains have switched to stabilize the ferroelectricity. After poling the ferroelectric polarization outward the TiO x layer (iii) two effects can explain the HRS: on one hand, the TiO x layer is depleted near the HZO interface, which increases the thickness of the insulating barrier. On the other hand, the polarization field increases the energy barrier height at the TiO x /HZO interface.
Analog resistive memories were fabricated with a CMOS compatible BEOL process. Ferroelectricity was obtained in a 4.5 nm-thick HZO layer crystallized with a moderate thermal budget of %375 C. A 3.5 nm-thick semiconducting TiO x interlayer was used to create an asymmetry in the energy profile of a TiN/HZO/TiN capacitor. The synaptic functionality (nonvolatility and plasticity) was further enhanced after a ferroelectric wake-up of the devices. Electrical characterization confirms that the resistive switching originates from the ferroelectric properties of the HZO layer. These preliminary results raise interest in further understanding the role of the oxygen vacancies in the conduction mechanisms and the polarization to enhance the memristive functionality of HZO diodes.

Experimental Section
Fabrication: A 200 nm of SiO 2 was deposited on an Si nþ substrate by plasma-enhanced chemical vapor deposition (PECVD) at 300 C. Then, 15 nm TiN was deposited in a plasma-enhanced ALD (PEALD) system using a tetrakis-(dimethylamino)titanium (TDMAT) precursor and N 2 /H 2 plasma at 300 C. Subsequently, 3.5 nm TiO 2 was deposited using TDMAT precursor and O 2 at 300 C, followed by 4.5 nm HZO that was grown in a www.advancedsciencenews.com www.pss-rapid.com process using alternating cycles of tetrakis-(ethylmethylamino)hafnium (TEMAH) and ZrCMMM ((MeCp)-2Zr(OMe)(Me)) at 300 C. The composition of HZO for these conditions was determined to be Hf 0.57 Zr 0.43 O 2 (not shown) by Rutherford backscattering (RBS) analysis. Finally, a capping layer of 10 nm TiN was additionally grown. The sample was then annealed at 375 C with a ms-FLA [20] and then transferred to a sputter chamber for the deposition of 100 nm W. Capacitors were defined by a optical lithography step and reactive ion etching (RIE) etch step of the W using a SF 6 /O 2 plasma. Characterization: GIXRD and XRR measurements were performed by a Bruker D8 Discover diffractometer equipped with a rotating anode generator. The electrical characterization was conducted on a Agilent B1500A semiconductor analyzer and an AixACCT TF Analyzer 2000.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.