Conference paper Open Access

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

Rodriguez Condia, Josie Esteban; Narducci, Pierpaolo; Sonza Reorda, Matteo; Sterpone, Luca


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      <creatorName>Rodriguez Condia, Josie Esteban</creatorName>
      <givenName>Josie Esteban</givenName>
      <familyName>Rodriguez Condia</familyName>
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      <affiliation>Politecnico di Torino</affiliation>
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    <creator>
      <creatorName>Narducci, Pierpaolo</creatorName>
      <givenName>Pierpaolo</givenName>
      <familyName>Narducci</familyName>
      <affiliation>Politecnico di Torino</affiliation>
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      <creatorName>Sonza Reorda, Matteo</creatorName>
      <givenName>Matteo</givenName>
      <familyName>Sonza Reorda</familyName>
      <affiliation>Politecnico di Torino</affiliation>
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    <creator>
      <creatorName>Sterpone, Luca</creatorName>
      <givenName>Luca</givenName>
      <familyName>Sterpone</familyName>
      <affiliation>Politecnico di Torino</affiliation>
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  <titles>
    <title>A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2020</publicationYear>
  <subjects>
    <subject>Duplication with Comparison (DWC)</subject>
    <subject>Fault detection</subject>
    <subject>General Purpose Graphics Processing Units (GPGPUs)</subject>
    <subject>Graphics Processors</subject>
  </subjects>
  <dates>
    <date dateType="Issued">2020-05-19</date>
  </dates>
  <language>en</language>
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    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/DDECS50862.2020.9095665</relatedIdentifier>
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  <version>1</version>
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  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;Open access version of the manuscript presented at DDECS2020 conference&lt;/p&gt;</description>
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      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/722325/">722325</awardNumber>
      <awardTitle>Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design</awardTitle>
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