Voltage Sag Compensation in Fourteen Bus System during Line Interruption Using Interline Dynamic Voltage Restorer

This paper deals with power quality improvement in fourteen bus system (FBS) using IDVR. Investigations were carried out to find the improvement of real and reactive power by employing IDVR during line outage condition. The closed loop responses of PI, PID and FL controlled systems are modelled and simulated using simulink and the results are obtained. Load flow studies were conducted for healthy system, FBS with line outage and FBS with line outage with inclusion of IDVR. The simulation studies indicate that, the voltage under line outage condition with IDVR is almost equal to the voltage under healthy condition. The Responses of closed loop systems with PI, PID and FLC are compared and the analysis shows the improvement in dynamic response in terms of settling time, rise time and peak time and reduces the steady state error. The advantages of proposed system is improved voltage stability, flexibility to control real and reactive powers and concluded that FLC based IDVR system had better time response. The prototype for four bus system with IDVR is modelled and the results are obtained.


Introduction
Nowadays, power electronics plays a vital role in transmission lines and industries. Because of the very sensitive and less tolerant equipment are used. Therefore for a short time, voltage sag occurs in these places. Voltage sag is created by connecting an additional load in parallel with the exiting load. Among the several novals, the dynamically voltage restorer is one of the power electronics devices which is technically advanced over economical for voltage sag mitigation in distribution system [1]. The DVR works by injecting ac voltage in series with the incoming supply voltage, the purpose of which is used to improve voltage quality. DVR involves injection of real and reactive power to the distribution system to compensate the voltage sag problems which determines the capacity of the energy storage devices. In order to meet the real power requirement an external energy storage is required especially for mitigating long duration voltage sag compensation, the maximum amount of real power which is supplied to the load is a deciding factor of DVR, while the reactive power is generated electronically by using VSI voltage injection from the DVR is an appropriate phase advanced with respect to source side voltage can reduce energy consumption. For some phase advance technique alone, energy requirement cannot be met [2]. Therefore for mitigating deep long duration sags, as it is merely a way of optimizing existing energy storage. By dynamically replenished the DC link of the DVR that can be capable of mitigating deep sags with long durations.
The interline DVR proposed in this paper is to introduce a new way that recovers the energy in the common variable DC energy storage. IDVR is the combination of different DVRs which protect the sensitive loads in various distribution feeders. These feeds are originated from different grid substations. These DVRs are connected to common DC link. The above proposed theory deals with the balancing problems in no of transmission lines at a given substation. In [3] IPFC, the real power is transferred directly between the compensating lines and the reactive power is transferred within each individuals lines. Similarly in IDVR transfer the real power  [4] and closed loop [5], which is used in the DVR applications. The above discussion does not deal with comparison of fourteen bus system with and without line interruption. The objective of proposed system is to compare the response with closed loop controllers using IDVR. The organization of the paper is as follows: Section II deals with configuration of IDVR. Section III provides the results of contingency analysis. Section IV compares the simulation results of closed loop controllers with IDVR. Section V shows the experimental setup.

Interline Dynamic Voltage Restorer System
The interline dynamic voltage restorer consists of four bus connected with two source supplying different load. If sag occurs in feeder 1, the compensating voltage reactive power supplied to the load through feeder 2 with IDVR. The above process is developed further by increasing the no of buses in order to increase real and reactive power for compensation. The fourteen bus system is developed with IDVR employing PI, PID and FUZZY controllers in closed loop. Hence this method provides had better time response. Consider two feeders supplying different load. Here voltage sag occurs in feeder 1, the load is disconnected from feeder 1 and it is supplied with IDVR. Simulation of voltage insertion is implemented by a voltage loss across series connected impedance and reactance. Magnitude of load voltage should not disturb by impedance insertion. To keeping the load voltage magnitude unvaried, the insertion of voltage having two components likely Vr real power and Vy reactive power. In real power absorption Vr is in phase according to their relative phasor and reactive power Vy takes place between the load voltage V L which it does not change the voltage magnitude. Figure 4 shows the equivalent circuit diagram of feeder with series voltage impedance injection. Figure 5 shows the phasor diagram of feeder.
Output Power is given by (2) Here (3) The power factor angle γ and maximum angle α will be unity. The maximum value for is given by (4) Absorbed real power from feeder resistance r is given by (5) Length cd is given by Capacitive reactance can be given as √ Substitute value in 7 equation we get

Results and Analysis
Contingencies are defined as potentially harmful disturbances that occur during the steady state operation of a power system. Load flow constitutes the most important study in a power system for planning, operation and expansion. The purpose of load flow study is to compute operating conditions of the power system under steady state. These operating

Normal Condition
Fourteen bus systems with IDVR under normal condition is shown in Figure 6. The voltage at bus 4 is shown in Figure 7 and its peak value is 4000V. The RMS voltage at bus 4 is shown in Figure 8 and its value is 2750V. The real and reactive powers at bus 4 are shown in Figure 9. The value of real power 2.5*10 5 W reactive power 2.6*10 4 VAR

Line 2 Open and IDVR Off Condition
The fourteen bus system with line 2 open and IDVR off condition system is shown in Figure 10. The voltage of bus 4 is shown in Figure 11 and its peak value is 3000V. The RMS voltage at bus 4 is shown in Figure 12 and its value is 2000V. The real and reactive powers at bus 4 are shown in Figure 13 and its value of real and reactive power is 1.5*10 5 W and reactive power is 1.7*10 4 VAR.   Figure  14. The voltage at bus 4 is shown in Figure 15 and its peak value is 3800V. The RMS voltages at bus 4 are shown in Figure 16 and its value is 2600V. The real and reactive powers at bus 4 are shown in Figure 17 and its value of real power is 0.225MW and reactive power is 0.023MVAR.

Closed Loop Response 4.1. Design of PI Voltage Controller
PI controller is mainly used to eliminate the steady state error resulting from P controller. However, in terms of the speed of the response and overall stability of the system, it has a negative impact.  The Simulink diagram of the closed loop controlled IDVR system with the PI controller is shown in the Figure 19. The AC output voltage of the CT is rectified using a controlled rectifier. The DC is converted into AC using a PWM inverter, and the output voltage of the inverter is injected using a transformer. The load voltage is sensed and it is rectified and compared with a

Design of PID Controller
PID controller has the optimum control dynamics including zero steady state error, short rise time, oscillation free and high stability. The necessity of using a derivative gain component in addition to the PI controller is to eradicate the overshoot and the oscillations occurring in the response of the system. One of the main advantages of the PID controller is that it can be used with higher order processes including more than single energy storage.
. Figure 24. Design of PID Controller Closed loop system with the PID controller is shown in Figure 25. The voltage across the load 3 and the load 4 are shown in Figure 26.The RMS voltage across the load is shown in Figure 27 and its value is 2500V. The new load is connected at 0.32 seconds and the voltage is compensated at 0.37 seconds.

Experimental Results
The hardware model of four bus system with interline dynamic voltage restorer and is shown in Figure 36.

Conclusion
The results of fourteen bus system with and without IDVR are modelled and simulated. FBS with line outage and inclusion of IDVR is also simulated. The change in voltage during line outage is only 0.3KV by including IDVR. The changes in real power and reactive power are 0.03MW and 0.003 MVAR respectively. The closed loop controlled compensation in fourteen bus system was achieved using PI, PID and FLC controllers. The comparison of the responses indicates that the FLC produces better dynamic response then PI and PID controlled systems. The steady state error of fourteen bus system with FLC controller is 56% less in comparison to proportional integrated controller. The prototype model for four bus system with IDVR is modelled and results are obtained and compared with simulation results. The FBS with proposed IDVR has benefits like improved voltage profile and power transfer ability. The disadvantage of IDVR is that it requires six IGBTs.
The scope of the present work is to study the power quality improvement in fourteen bus system with IDVR. The power quality improvement in thirty three bus system will be investigated in future