Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single-and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: ($i$) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-R bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond-breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.


I. INTRODUCTION
Hot-carrier degradation (HCD) accelerated by self-heating (SH) was highlighted to be the most detrimental reliability concern in modern ultra-scaled field-effect transistors (FETs) with confined architectures, such as nanowire (NW) and FinFETs [1][2][3]. This is because in modern FETs device dimensions reduce faster than the operating and stress voltages, thereby resulting in high electric fields. On top of this, channel lengths in scaled devices are comparable to (or even shorter than) the mean free path of carriers and therefore electrons/holes dissipate much less energy due to scattering events. These factors lead to substantial acceleration of carriers even in decananometer transistors and hence to prominent hotcarrier degradation. As for the intimately related phenomenon of bias temperature instability (BTI), it was reported to be less destructive in ultra-scaled transistors than HCD [1]. Moreover, special measures how to control and alleviate BTI were recently proposed and validated [4,5]. These techniques are based on shifting the defect band towards the energy range inaccessible for the carriers by tuning the work-function and introducing dipoles between SiO 2 and high-k layers. However, comparable approaches to mitigating HCD were not elaborated so far and thus better understanding of the physical mechanisms responsible for HCD should help us develop such approaches.
In confined structures, such as FinFETs and NWFETs, narrow channels are surrounded by dielectric layers with a low thermal conductivity and therefore heat dissipation in these channels is hindered. As a consequence, local lattice temperature in a nanowire/fin channel can be substantially higher than ambient temperature. This effect is called "selfheating" [6]. On the other hand, it is widely acknowledged that in short-channel MOSFETs HCD becomes stronger at elevated temperatures [7][8][9][10], as opposed to long-channel transistors where HCD is weaker if a device is heated [11][12][13]. Therefore, self-heating enhances hot-carrier degradation and an accurate predictive model for HCD should consider the impact of SH on this detrimental phenomenon.
Although there are a number of carefully validated physical models [10,[14][15][16][17][18] for HCD as well as physics-based simulation approaches to SH [6,19,20], they have not been combined within a single simulation framework. To the best of our knowledge, the attempts to model the impact of SH on HCD published so far are empirical and phenomenological [21][22][23][24].
However, HCD itself is a very intricate effect, which stems from rupture of Si-H bonds at the Si/SiO 2 interface induced by hot and cold carriers via single-and multiplecarrier (SC-and MC-) mechanisms of bond dissociation [14,[25][26][27][28]. Understanding the fashion of how SH impacts the rates of these mechanisms is a non-trivial task, which is, however, of high importance because switching from harsh stress regimes to the operating conditions is accompanied by reduction of the relative role of the SC-mechanism [10]. As a result, a predictive model for HCD should accurately capture this trend, which is made even more complex by SH. Since empirical/phenomenological models are not capable of reproducing this behavior, one needs to thoroughly describe the physical picture behind HCD accelerated by SH.
To bridge the gap between models for HCD and SH we extend our hot-carrier degradation simulation framework and model carrier transport, the bond-breakage rates, and degradation of transistor characteristics considering non-uniform temperature distributions due to SH. To validate the model we use hot-carrier degradation data acquired in p-channel NWFETs.

II. DEVICES AND EXPERIMENT
We employed p-channel gate-all-around NWFETs on Si. Each of these devices is designed up of 44 (22×2) stacked parallel NWs with a diameter of 9 nm and a gate length of 100 nm; the devices are sketched in Fig. 1 0.7 and 2.1 nm, respectively. More details of the fabrication process and device architecture can be found in [29].
The NWFETs were subjected to hot-carrier stress at three different combinations of voltages: Stresses were applied for ∼500 ks at ambient temperature of 298 K. To assess HCD we recorded relative changes of the saturation drain current ∆I d,sat as a function of stress time t and summarized them in Fig. 2. Note that I d,sat corresponds to V gs = V ds = -V dd (V dd = 0.9 V is the operating voltage).
During measurements, special attention was paid to ensure that the degradation is driven by HCD and BTI does not make a significant contribution. For this, we checked whether the degradation has a recoverable component and found that recovery can be neglected; this proofs that BTI, which is mainly due to trapping of carriers by oxide traps, can be indeed disregarded. Moreover, we stressed in a regime with relatively high drain voltage of V ds > 1.0 V in combination with room ambient temperature T = 298 K to further weaken possible contributions of BTI. In this regime the degradation is dominated by a superposition of SC-and MC-mechanisms of Si-H bond dissociation [10,30]. More details of our measurements are given in [31].

III. THE MODELING FRAMEWORK
We extend our model for hot-carrier degradation (sketched in Fig. 3), which was validated against HCD data measured across a wide class of transistors [30,[32][33][34], in the manner as to incorporate a non-uniform distribution of lattice temperature T resulting from SH. Note that in our recent publication [35] the model was demonstrated to reproduce HCD in the same pNWFETs but the impact of SH was not addressed.
Within this model, HCD is assumed to be driven by dissociation of Si-H bonds at the Si/SiO 2 interface. Bond rupture can be induced by a solitary highly energetical carrier which energy higher than the bond-breakage energy (E a ∼2.6 eV [36]). This mechanism is called "single-carrier mechanism" (Fig. 4). If V ds < E a /|e| (|e| is the electron charge) the concentration of these energetic carriers is low and the SCmechanism has a negligible rate. However, HCD can still be strong even in ultra-scaled devices because in this case bond rupture is driven by the MC-process, which is based on the multiple vibrational excitation of the bond [14,25,26,37], see Fig. 4. The SC-and MC-mechanisms are two alternative pathways of the same reaction converting the defect precursors (Si-H bonds) into the electrically active defects (P b -centers) and these processes are coupled. Moreover, in ultra-scaled MOSFETs with stress drain voltages in the range of 1.2-2.0 V  the most probable scenario of bond dissociation is related to initial pre-heating the bond via inducing its vibrational modes by cold carriers, followed by its rupture by a single hot carrier [15,38]; this scenario is sketched in Fig. 4, right panel. Within this picture, the potential barrier separating an excited (but still bonded) level is reduced as compared to the bonding energy E a by the energetical position of this level. Therefore, the probability that the carrier ensembles contains particles possessing this energy or higher can be substantially high.
To calculate the rates of SC-and MC-mechanisms one needs to know how the carriers are distributed over energy; this infor-  An important aspect of the modeling framework is the device architecture, which includes device dimensions and parameters of the doping profiles. This information is obtained with Sentaurus Process [41], coupled with the device and circuit simulator MINIMOS-NT [42] used within the GTS framework [43]. Such coupling is needed to calibrate the process and device simulators self-consistently by reproducing current-voltage characteristics of the undamaged transistor. MINIMOS-NT uses drift-diffusion and hydrodynamic approaches to an approximate solution of the BTE, which are not accurate enough for carrier transport modeling (for instance, we showed that versions of our HCD models based on these transport models fail to correctly represent degradation characteristics [44]). However, these models can be used to simulate current-voltage characteristics of pristine and degraded devices with a reasonable accuracy. For nanowire channels with a diameter of 9 nm, quantum effects should be taken into account and we use therefore the density gradient and improved modified local density approximation methods [45] implemented in MINIMOS-NT.
Based on the carrier DFs we calculate the rates of the coupled SC-and MC-processes and evaluate the interface state density N it for each coordinate at the interface and for a given stress time step t. The obtained concentration N it is used in the device and circuit simulator MINIMOS-NT to model the characteristics of the degraded device. Note that the effect of charged interface states is twofold, i.e., they perturb the electrostatic potential and scatter carriers, thereby reducing the carrier mobility. Both aspects are captured in MINIMOS-NT. At this stage, possible errors in calculations of the drain current with drift-diffusion and hydrodynamic models are not so critical because we consider relative changes in the drain current, i.e. at each times step t the ∆I d,sat (t) value is normalized to the ∆I d,sat (t = 0).
In our recent publication [35], we evaluated carrier DFs for the same device and stress conditions assuming that lattice temperature does not vary with the coordinate. Now, in the extended approach, we calculate carrier DFs taking into account temperature distributions in the NWFET (Figs. 5-6). To obtain these T spatial profiles we use the device simulator MINIMOS-NT, which solves the lattice heat flow equation coupled with the approach for solving the BTE for carriers. The heat generation term enters the lattice heat flow equation and its particular form depends on whether the drift-diffusion or the hydrodynamic approach to the BTE solution for carriers is used. For the simulations conducted in this work, we used the the drift-diffusion approximation with the heat generation term equal to the Joule heat. In the hydrodynamic approach this term is evaluated using the energy relaxation times.
Let us emphasize that the most thorough description of HCD coupled with SH requires a self-consistent solutions of the BTEs for carriers and phonons. This solution, however, requires quite substantial computational resources even within the current implementation, where instead of the full solution of the phonon BTE we use the simplified approach implemented in MINIMOS-NT. Therefore, we solve the coupled drift-diffusion and lattice heat flow equations only once, obtain the temperature distribution, and compute the carrier DFs based on this distribution.
Another important ingredient taken into account in the extended model is the temperature dependency of the lifetime of the stretching vibrational mode of the Si-H bond. Note the Si-H bond has stretching and bending vibrational modes but bond rupture occurs via the stretching mode, as it was discussed in sufficient detail in [10,46]. Andrianov et al. [47,48] have shown that vibrational lifetime is a decaying function of T , i.e. at higher T an excited Si-H bond returns faster to the ground state and this reduces the MC-process rate [14,25,38]. In one of our publications [10] we discussed in sufficient detail that the dependence of vibrational lifetime on T is an important factor, which should be considered while modeling HCD and its temperature behavior.
Dissociation of a Si-H bond can occur from excited bonded states by a superposition of (i) the contribution given by carriers which deliver a portion of energy higher than the potential barrier separating this bonded state and the transport mode and (ii) thermal activation over this potential barrier (see Fig. 4). In this case the bond-breakage rate is evaluated as where ω th being the attempt frequency for thermal activation, i, E i the index of the excited level and its energetical position, and k B the Boltzmann constant; a more detailed description is provided in [30,38]. In (1) the first term corresponds to thermal breakage of the bond, while the second term represents the SC-process rate from an excited level i. On can see that the first term is a rapidly increasing function of T . The rate I SC,i is calculated as with f (E), g(E), σ 0 (ε), and v(E) being respectively the occupation number as a function of energy E, the density-  The SC-process triggered by a solitary hot carrier dominates HCD in long-channel/high-voltages devices, while the MC-process becomes more important at low operating/stress voltages and high current densities. In modern scaled MOSFETs HCD is driven by superposition of these two mechanisms.
of-states, the energy dependent cross section of the bondbreakage reaction (σ 0 is a fitting parameter of the model), and the carrier velocity; the exponent p it,SC is equal to 11. It is noteworthy that changes in the carrier DF (the product f (E)g(E)) -due, for example, to SH -can result in substantial changes in the bond-breakage rate I SC,i . In the extended model, the interplay between all the aforementioned components is considered. Fig. 5 summarizes temperature distributions evaluated for three stress conditions; these distributions are shown for the channel and source/drain extensions. First of all, one can see that lattice temperature can be substantially higher than ambient temperature and this effect becomes more pronounced at higher drain voltages. (Let us remind that the gate voltage is fixed and equal to -1.3 V.) This is because at higher values of V ds and a fixed V gs the density of power dissipated in the transistor channel is higher, thereby making the effect of self-heating stronger. Another important feature pronounced in Fig. 5 is that lattice temperature peaks in the drain end of the channel and this trend is similar to one of the main peculiarities of HCD, i.e. its strong localization near the drain. In both cases of SH and HCD the carriers need to travel some distance in the transistor until they are accelerated to energies high enough to substantially heat the devices or trigger a bondbreakage event. For the sake of better visibility, we made one dimensional cuts of temperature distributions (Fig. 5) at the Si/ SiO 2 interface and obtained temperature dependencies vs. the coordinate z in the source-drain direction, which are shown in Fig. 6 for all stress conditions. Note that as the channel has a cylindrical symmetry, these one-dimensional temperature profiles are the same for different values of the coordinates x and y in the plane perpendicular to the source-drain direction. Fig. 6 shows exactly the same trends as Fig. 5: the temperature peak becomes higher at higher V ds and is situated near the drain. Fig. 7 shows a series of hole DFs computed with and without the impact of distributed temperature for V gs = -1.3 V and V ds = -1.6 V and plotted for z = 50 nm (exactly in the middle of the device), z = 75 nm, and z = 100 nm (the drain end of the channel). Let us note that the hole DFs are substantially shifted from equilibrium, i.e., they are visibly non-Maxwellian. Nevertheless, the Maxwellian tail can be seen at higher energies. However, when we proceed closer to the drain (where carriers are hotter than in the center of the NWFET) this tail shifts to even higher energies and in general the DFs transform become more non-Maxwellian. Another important peculiarity is that DFs obtained considering the impact of SH are shifted towards higher energies with respect to those computed neglecting SH. Based on this trend, one can conclude that the SC-process induced portion of the damage should have a higher rate due to SH (as can be seen from formula (2)) and therefore HCD in general is enhanced by SH. At a first glance, the reported behavior of the hole DFs seems counterintuitive because the scattering mechanisms -which suppress the high energetical fraction of the carrier ensemble -become more efficient at elevated temperatures, thereby weakening HCD. However, the segment where the DF values increase with energy (for instance, for the drain DFs this increase corresponds to the energy range of [0-0.7] eV) is due to the interactions of carriers with phonons. Due to the temperature activation of this process the aforementioned segment becomes wider if SH is considered, thereby leading to the shift of the high-energetical tails of the DFs. This effect is consistent with the scenario reported by Abramo et al. [49], in which carriers can gain energy from phonons if the number of adsorbed phonons exceeds the number of emitted ones and these interactions can be responsible for enhancement of HCD in sub-0.1 µm transistors.

IV. RESULTS AND DISCUSSION
From Fig. 2 one can see that ∆I d,sat (t) traces simulated without the impact of SH on HCD are lower compared to those obtained considering this impact. The difference in the ∆I d,sat changes is especially pronounced at short stress times. Such an observation appears consistent with our previous findings that short-term HCD is determined by the near-drain portion of the damage induced by the single-carrier process (accelerated by the multiple-carrier mechanism though) [32,33]. Our current modeling results suggest that SH makes the most prominent impact on the single-carrier process accelerated by the vibrational excitation of the bond induced by cold carriers, see Fig. 4 and Eqs. (1) and (2), and therefore the impact of SH on ∆I d,sat changes are most prominent for short stress times. Nevertheless, one can see that neglecting SH results in substantial HCD underestimation also at longer stresses. It is noteworthy, however, that larger values of ∆I d,sat obtained when SH is taken into account stem not exclusively from the behavior of hole DFs but also from the T dependence of the Si-H bond vibrational lifetime and thermal contribution to bond rupture, as discussed in Section III. Finally, one can see that the model can cover the degradation traces with good accuracy.

V. CONCLUSIONS
We presented and validated a framework for modeling coupled self-heating and hot-carrier degradation; this framework is physics-based. The impact of SH on HCD is a superposition of features of carrier transport at distributed temperature, the temperature dependency of the vibrational lifetime of the bond, and the thermal contribution to bond dissociation. To obtain lattice temperature changes due to SH we solved coupled drift-diffusion and heat flow equations. The impact of nonuniformly distributed temperature on carrier transport was shown to shift carrier energy distribution functions towards Fig. 6. Dependencies of lattice temperature at the Si/SiO 2 interface on the lateral coordinate z obtained for three stress conditions. The source corresponds to z = 0, while the drain is at z = 100 nm.