A 300 GHz CMOS Transmitter Front-End for Ultrahigh-Speed Wireless Communications

This paper presents a 300 GHz transmitter front-end suitable for ultrahigh-speed wireless communications. The transmitter front-end realized in TSMC 40 nm CMOS consists of a common-source (CS) based doubler driven by a two-way D-band power ampliﬁer (PA). Simulation results show that the two-way D-band PA obtains a peak gain of 21.6 dB over a -3 dB bandwidth from 132 GHz to 159 GHz. It exhibits a saturated power of 7.2 dBm and a power added efﬁciency (PAE) of 2.3%, all at 150 GHz. The CS based doubler results in an output power of 0.5 mW at 300 GHz. The transmitter front-end consumes a DC power of 205.8 mW from a 0.9 V supply voltage while it occupies an area of 2.1 mm 2 .


INTRODUCTION
According to the current trend, frequency used for wireless communication will reach terahertz band in 2020. Unallocated frequency region beyond 275 GHz with vast bandwidth can be potentially utilized for ultrahigh-speed wireless communication. In particular, 300 GHz band is attractive since propagation decay in air around 300 GHz is relatively low. However, since studies on terahertz wireless communication including 300 GHz band are still in early stage when only a few transceivers operating above 275 GHz were reported [1] [2] [3]. Since the maximum operating frequency or unity-power-gain frequency, f max , of the n-type MOSFET even with advanced CMOS process is below 300 GHz, realization of 300 GHz RF front-end is challenging. One solution is to use frequency multipliers. A 300 GHz CMOS RF front-end was reported using a tripler [4]. However, the tripler generates not only the desired RF signal but also the higher-order spurious. As a result, the RF signal may be distorted by a higher-order spurious. On the other hand, since quadratic nonlinearity of a MOSFET is stronger than its cubic counterpart, a doubler can generate higher output power than a tripler does.
In this paper, we are going to present the designs and simulations of a 300 GHz transmitter front-end as illustrated in Fig. 1. It includes the CS based doublers (DBLs) driven by the two-way D-band PA. When the doubler is employed, the 300 GHz output signal can be generated from the 150 GHz input one. The paper is organized as follows. Section 2 introduces the architectures of the proposed 300 GHz transmitter front-end including detailed descriptions of circuit topologies. The simulation results are presented in section 3 and conclusions are given in the last section.

DESIGN OF 300 GHz TRANSMITTER FRONT-END 2.1. Transmission Lines and Rat-Race Balun
The 300 GHz transmitter front-end is designed using TSMC 40 nm 1P10M CMOS GP process. Its back end consists of 10 copper layers and a top aluminum redistribution layer (RDL). The cross-view of grounded coplanar wave-guide transmission lines (GCPW-TLs) are depicted in Fig. 2 [5]. The GCPW-TL with the characteristic ulation by ANSYS HFSS shows that the attenuation constant, α, of the 50 Ω and 71 Ω GCPW-TLs is 1.0-1.4 dB/mm and 1.2-1.6 dB/mm at 100-150 GHz, respectively. The shunt stubs of the inter-stage networks are arranged adjacent across a common GND wall, and the space between the GCPW-TLs is 17 µm. The near-end and far-end crosstalk simulated by EM simulation are below -30 dB and -34 dB at 100 GHz and 250 GHz, respectively. It indicates that the cross-coupling between stubs is negligible. As illustrated in Fig. 3, the double rat-race balun composed of the 71 Ω GCPW-TLs is designed for generating the differential signal from the single-ended one. The length of the GCPW-TL unit of the double rat-race balun is 300 µm which is equivalent to λ/4 at 150 GHz (λ is the wave length). The compact design is realized by folding the GCPW-TLs and sharing the GND wall. ISSN: 2088-8708

Two-Way D-Band Power Amplifier
The circuit schematic of the proposed D-band PA is shown in Fig. 4. It includes an input matching network, an output matching network, three fully differential amplifying stages and inter-stage matching networks. For bandwidth enhancement, multi-stage matchings using capacitors and inductive GCPW-TLs are adopted. The series capacitors and shunt GCPW-TLs form 4th-order high-pass filters at the input ports. The outputs of the PA are directly matched to the inputs of the doubler. The inter-stage matching networks are based on PI networks for wideband performance. All of the capacitors also act as coupling capacitors while the DC bias voltages are applied across the GCPW-TLs. The bias voltages are common to all amplifying stages. The shunt stubs composed of 71 Ω GCPW-TLs are arranged regularly with sharing GND walls. The connection between the MOSFETs, MOM capacitors and GCPW-TLs are made by the 8th to 10th metal layers. The lengths of the GCPW-TLs and the MOM capacitor values are determined by a nonmetric optimization process taking into account the models of MOSFETs, MOM capacitors and GCPW-TLs. The far end of each shunt stub is terminated by a wideband decoupling power line with very low characteristic impedance (the 0 Ω TL). The internal negative feedback path caused by the parasitic gate-drain capacitor, C GD limits the power gain and reverse isolation, and potentially causes instability. In order to improve the stability without compromising the IJECE ISSN: 2088-8708 2281 gain of the MOSFET, the internal feedback in the transistor has to be reduced. An elegant technique to accomplish this is to neutralize C GD in a differential pair by using cross coupling capacitors [6]. Fig. 5a shows the core of the amplifier that is a fully differential pair with capacitive neutralization. The cross coupling capacitor, whose value is 16.1 fF, is determined to obtain high gain. Fig. 5b reveals the parasitics associated at each node of the amplifier core. The parasitic components are extracted using bond-based design which is a measurement-based design approach to avoiding the difficulty associated with layout parasitics when ordinary layout parasitic extraction (LPE) tools used for chip design do not extract inductances. The two-way PA is formed by connecting two D-band PAs in parallel as depicted in Fig. 1. The driver amplifier (DA) at the input is employed as the pre-amplifier before the input power is divided by the double rat-race balun. The DA has a similar topology as the D-band PA does. It consists of four fully differential amplifying stages with cross-coupling capacitors. Many-stage amplifiers for terahertz frequencies tend to occupy a large area since interstage matching networks consist typically of several passive devices that are much large than MOSFETs. To realize cost-effective chips, area reduction is important. In order to reduce the area of the amplifier, we proposed the "fishbone layout" [7]. In this technique, GCPW-TL stubs used in matching networks are arranged regularly at narrow spacings, and the GCPW-TLs themselves are designed to be narrow, thereby reducing the footprint.

300 GHz CS Based Doubler
As the name suggest, the 300 GHz CS based doubler exploits the quadratic nonlinearity of the MOSFET. It upconverts the signal at the output of the D-band PA into RF signal at 300 GHz frequency band. The main reason using active frequency doubler is that it can achieve conversion gain over broad bandwidth while getting also good DC to RF efficiency. The complete circuit of the proposed doubler with all component values are given in Fig. 6. The same as power amplifiers, the active frequency multipliers work in different classes. In this design, the doubler is biased to operate in an equivalent class-AB power amplifier where it is very stable and have good gain, efficiency and output power. The doubler generates harmonics by rectifying the sinusoidal input signals when is biased near its pinch-off, and the input sinusoids turn the MOSFETs on over part of their cycles. Due to the balanced topology, the even harmonics are generated in phase thus being summed up while the odd harmonics are generated out of phase thus being suppressed. The outputs are tuned to the second harmonic while other harmonics including the fundamental frequency are further suppressed by the output PI matching networks. The second harmonic signals leaked through ISSN: 2088-8708 the MOSFETs to the input ports are shorted by using λ/2 short stubs. The inputs of the doubler are conjugate-matched to the optimal loads of the preceding D-band PA. Figure 6. The proposed 300 GHz CS based doubler.

SIMULATION RESULTS
Simulation results of the 300 GHz transmitter front-end for TSMC 40 nm CMOS technology are achieved using the Cadence's Virtuoso Analog Design Environment. Circuit design at very high frequencies involves more detailed considerations than at lower frequencies when the effect of parasitic capacitances and inductances can impose serious constrains on achievable performance. Thus, all components used for simulation are RF models provided by TSMC. Fig. 7 shows the simulated S-parameters of the two-way D-band PA. S 11 remains below -7 dB while S 22 is less than -10 dB over the -3 dB bandwidth from 132 GHz to 159 GHz. Both input and output return loss indicate wideband performance. The D-band PA achieves a peak gain of 21.6 dB over the band of interest. The reverse isolation is lower than -140 dB (not shown in the figure). A high reverse isolation guarantees high stability for the PA. Fig. 8 and Fig. 9 plot the output power and PAE versus input power, respectively. At 150 GHz, the designed PA obtains a saturated power of 7.2 dBm and a peak PAE of 2.3% at -6 dBm input power. The output referred 1 dB compression point (OP1dB) is 4 dBm. The two-way PA consumes a power of 199.4 mW from a 0.9 V supply voltage. Fig. 10 shows the simulated S-parameters of the 300 GHz transmitter front-end. As can be seen in this figure, both input and output return loss indicate good matchings. Fig. 11 and Fig. 12 show the output power of the transmitter versus input power and output frequency, respectively. At 150 GHz input frequency, the transmitter exhibits a saturated power of -2.2 dBm. It obtains an output power of -2.8 dBm which is equivalent to 0.5 mW at 300 GHz and covers a -3 dB bandwidth from 274 GHz to 323 GHz. The harmonic power levels are plotted in Fig. 13 where the odd harmonic levels are very low due to the balanced structure of the CS based doubler. Fig. 14 shows the layout of the 300 GHz transmitter front-end. It occupies an area of 2.1 mm 2 including probe pads. The transmitter consumes a power of 205.8 mW from a 0.9 V supply voltage. Table 1

CONCLUSIONS
In this paper, we have presented the designs and simulations of the 300 GHz transmitter front-end targeted for ultrahigh-speed wireless communications. The two-way D-band PA obtains the peak gain of 21.6 dB, the saturated power of 7.2 dBm and the PAE of 2.3%. The CS based doubler results in the peak output power of 0.5 mW at 300 GHz while covering the -3 dB bandwidth from 274 GHz to 323 GHz. Supplied by the 0.9 V supply voltage, the transmitter front-end consumes the DC power of 205.8 mW while it occupies the area of 2.1 mm 2 .