TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET

Received Feb 24, 2017 Revised Apr 28, 2017 Accepted May 27, 2017 This article presents extraction of small signal model parameters and TCAD simulation of novel asymmetric field plated dual material gate AlGaN/GaN HFET first time. Small signal model is essential for design of LNA and microwave electronic circuit by using the proposed superior performance HFET structure. Superior performances of device are due to its dual material gate structure and field plate that can provide better electric field uniformity, suppression of short channel effects and improvement in carrier transport efficiency. In this article we used direct parameter extraction methodology in which S-parameters of device were measured using pinchoff cold FET biasing. The measured S-parameters are then transformed into Y-parameters to extract capacitive elements and then in to Z-parameters to extract series parasitic elements. Intrinsic parameters are extracted from Y-parameters after de-embedding all parasitic elements of devce. Microwave figure of merits and dc performance are also studied for proposed HFET. The important figure of merits of device reported in the paper include transconductance, drain conductance, current gain, transducer power gain, available power gain, maximum stable gain, maximum frequency of oscillation, cut-off frequency, stability factor and time delay. Reported results are valdated with experimental and simulation results for consistency accuracy. Keyword:


INTRODUCTION
Due to unique properties of GaN material, it is possible to obtain large current densities in GaNbased HFETs [1], [2]. GaN based devices are also very useful for high frequency high temperature microwave applications such as radar systems [3], [4]. In the recent past, studies have been done on asymmetric MOSFETs [5], junctionless FETs [6] and dual material gate AlGaAs/GaAs HEMTs structures that uses two metals of different work functions [7]. Since analytical models help us to understand internal solid state device physics thus expected to be consistent with physical behavior of device. An accurate small signal model of HFET is extremely valuable for designing of important active circuits generally used for high frequency applications [8][9] These small signal compact models define physical characteristics and various limitations of active devices accurately [11], thus used for design of low noise power amplifiers by electronics and microwave engineers in industry. Small signal models of advanced devices are needed for CAD based simulations [12] for analysis and validation of newly developed device structures [13]. In present scenario, analytical models are much exploited for getting true feedback about optimization of fabrication process in semiconductor industries [14], [15]. In past most of small signal models developed for conventional HEMT structures are based on various approaches of device modelling [16], [17]. One of initial kind of detailed small signal  Dambrine, et al [18]. In recent past many researchers have developed variety of techniques and methods according to their used material system and conventional device structures [19], [20]. Requirement for development of small signal model for DMG AlGaN/GaN HEMT structure is felt since long but no such model for enhanced device structure is reported in recent past. In this paper we proposed small signal model for DMG GaN HFET structure incorporating field plate that can be exploited for advanced microwave circuit designs and for CAD based simulations.
It is possible to classify some existing modeling methods in three broad categories: whole optimization, partial optimization [21] and direct extraction methods [22], [23]. For the propoed DMG AlGaN/GaN HFET, the direct parameter extraction approach is used as it provides better consistency between parameter values and physical structure of device. This approach also facilitates extraction process to run faster than other techniques described earlier. Extraction is carried out using low as well as higher frequency as cold FET structure thus assures higher extraction accuracy [24]. Extracted small signal model parameters and dc as well as ac simulation results can provide clear insight about use of proposed device for microwave ranges of frequencies.

DEVICE STRUCTURE AND MODEL FORMULATION 2.1. Device Structure for Parameter Extraction and TCAD Simulations
Self explanatory schematic view of device structure of dual channel dual material gate Al 0.3 Ga 0.7 N/ GaN HFET is shown in Figure 1(a). In the proposed unique device the dual material concepts are based on previously fabricated devices by W. Long et al. [7]. Epitaxial layers of HFET were grown by MOCVD on a 2.5-inch sapphire substrate. Drain and source terminal ohmic contacts were formed by Ti/Al/Ni/Au metal stacks, followed by rapid thermal annealing at 884ºC for 50 seconds in nitrogen environment. Dual material gate was e-beam defined keeping total gate length of 1µm. Ni/Au metallization process was used to form dual metal gate Schottky contacts with the AlGaN cap layer. A Si 3 N 4 surface passivation layer was deposited using PECVD. In order to reduce source inductance via-holes were formed using plasma dry etching. Field plate is formed to increase E-field uniformity that further reduces current collapse in device (Li, et al., 2016).
For completing the fabrication process of the device using 100µm 2 gate area a standard gold plated air brdge process was used. Metals M 1 (Au) and M 2 (Ni) having work functions ϕ M1 (=5.3eV) and ϕ M2 (=4.4 eV) respectively define dual metal gate with width W (=100 m) for the device. A 3nm AlGaN cap layer forms interface between n-Al 0.3 Ga 0.7 N layer of 18 nm thickness that is followed by UID AlGaN spacer layer of 3 nm thickness. Purpose of introducing UID AlGaN spacer layer is to reduce ionized impurity scattering. A 2μm thick GaN channel layer is used to form heterointerface that creates 2-DEG conductive channel in the device. Sapphire substrate is used for device structure as it can withstand higher operating temperature as a power switching device. represent source, drain and gate electrodes inductances respectively. C pd, C pg, and C pgd, represent device contact pad capacitances between drain-source, gate-source and gate drain respectively. C pdi , C pgdi , and C pgi are inter-electrodes capacitances between drain-source, gate-drain and gate-source respectively. R gs and R gd represent input and output channel region resistances. C ds , C gs , and C gd , represent intrinsic capacitances between drain-source, gate-source and gate-drain respectively. g ds and g m represents drain conductance and transconductance of device. The g m V gs in small signal model represent current generator in the output circuit, where V gs represents as gate to source voltage with a phase shift of e -jωτ . Symbol (τ) represents transit time through the velocity saturated region of the 2DEG-channel. The ω is angular frequency (rad/sec) of the applied RF signal at gate terminal of device.

Method for Parameter Extraction
Parameter extraction is performed by using direct method as suggested by Minasian [25] and later modified by Dambrine et al [18] and Berroth and Bosch [26]. Initially S-parameter extraction is carried out for shunt extrinsic elements of device under pinch off mode of biasing keeping frequency with in 5GHz range thre after for series elements at higher frequency range. These measured S-parameters are then successively transformed into Y-parameters and then in to Z-parameters in order to obtain values of all the shunt and series parasitic elements. Again after de-embedding of all the parasitic elements, the intrinsic Yparameters are obtained. At the end intrinsic elements are derived by separating real and imaginary parts of intrinsic Y-parameters.

Extrinsic Parameters Extraction and Analytical Expressions
The extrinsic capacitive elements are extracted from imaginary Y-parameters under pinch-off condition (V gs < V pinch-off and V ds =0V). Now the equivalent voltage controlled current source forming intrinsic part of device is disabled. In case of low frequency input in the range of 5 GHz, the whole circuit can be treated as a capacitive network as shown in Figure 2(a). Following Equations can appropriately describe the relationship between extrinsic capacitances and imaginary parts of the Y-parameters under pinched off condition: In Figure 2(b) imaginary Y-parameter curves with in frequency range of 5GHz are shown. It is clear that Y-parameters have sufficient linearity at low frequency range (below 5GHz). Therefore, the parasitic capacitances can be safely extracted from the slop of imaginary Y-parameter curves. Here, C gsp , C gdp and C dsp provide intrinsic substitute of pinched of cold FET part of circuit. Assumption is made as [27] 12 dsp pd CC  Due to asymmetric device structure ratio of gate-drain spacing with that of gate-source spacing is 1.5. So the relationship of its capacitance can be expressed as Since size and shape of all pads are same so these capacitances can be treated as equal in value as Considering device structure C dsi is larger than pad capacitances. An assumption is made here as Under high frequency small input signal with gate forward biased (V gs ≥0) drain at zero potential (V ds =0V), small signal equivalent circuit is reduced as in Figure 3(a). In this condition gate leakage current (I g ) flows and internal device capacitances are shunted with conductance open circuited. Since all inter electrodes capacitances are inside of parasitic resistance so no approximation needed by keeping precision of compact model as intact. At this specific bias point, the following simplified Equations of Z-parameters are valid: In the above expressions, Rc, represents channel resistance and r represents ratio of channel resistance between gate to drain and gate to source i.e (r=R cgd / R cgs ). As per our proposed asymmetric device structure value of r is 1.5 considering source and drain separation from gate. C df , C gf and C sf , represent fringing capacitances resulting at drain, gate and source terminals respectively in cold FET high frequency equivalent circuit. Also kT/qI g in Equation (8) gives the differential resistance of the Schottky diode. In this expression, , K and T represent ideality factor of diode, Boltzmann constant and absolute ambient temperature respectively. Now by transforming Y-parameters in to Z-parameters, R g , R s and R d can be extracted from the Re (Z ij ) curves. By multiplying ω by imaginary parts of impedances, following expressions are obtained 2 11 11

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The ωIm(Z ij ) versus ω 2 plot is shown in Figure 3(b). Slop of these curves can be used to extract values of L g , L d and L s respectively. The imaginary part of the Z-parameters increases linearly with frequency but real part is independent from frequency variations. The value of R c is determined by forming following Equations by using pinch off Z-parameters as follows 22 - Also, from Equation (10) it is noted that 22 Re( ) 22 22 -

Intrinsic Parameters Extraction and Analytical Expressions
The intrinsic part of the device can be described by the following Y-parameters: where 2 1 u   (21) gs gs Therefore, the value of individual intrinsic parameter can be derived from Equations (17)   Extrinsic parameters as listed in Table 1, are extracted for 1x100µm 2 gate size device at ambient temperature (T) =305K. The capacitances are extracted for f L =0 to 5GHz, V gs = -8V, V ds =0V. For series inductances and resistances, f H =5 to 200GHz, V gs = -3V, V ds =0V is applied. Intrinsic parameters as listed in Table 2, are extracted from S-parameters measured at Vds=10V and Vgs= -1V, T=305K, f H =5 to 200 GHz. These parameters are also validated with recently reported results [28] [29].

Characterization and Modelling of Microwave Figures of Merits
Microwave performance of device was characterized using Agilent Technologies N5230A network analyzer. The system calibration ensured with a short-open load-through calibration standard. Figure 4 shows block diagram for extraction of S-parameters by using two port matching lossless output and input network. Circuit shows E s , Z s and Z L as excitation source, source impedance and load impedances respectively. P i , P A , P L and P avo represent input power, available input power, power delivered to load and available power at output respectively.
Paper models following figure of merits for proposed unique device P Transducer power gain (G TP ) Where k represents stability factor of device and obtained as Cut off frequency (f t ) for DCDMG AlGaN HEMT at which short circuit current gain rolls off to 0 dB can be obtained as Maximum oscillation frequency (f max ) can be determined by using intrinsic and extrinsic components of device as Figure 4. Block diagram of matching impedance network for s-parameters measurement

RESULTS AND DISCUSSIONS
We used MATLAB and Silvaco TCAD ISE [13] as modeling and device simulation tools respectively for our research work. GaN material based device models (print srh, albrct.n) and polarization based models are applied for considering piezoelectric and spontaneous polarization effects at the heterointerface of the GaN device structure as described in ATLAS user manual of Sivaco TCAD. Figure 5(a) shows comparison of simulated [13] and experimental [30] output current voltage characteristics of device for various gate-to-source voltages (V gs ). Figure 5(b) shows comparison of simulated and experimental [30] input characteristics of DMG AlGaN/GaN HFET. It is evident from graph that gate has effective control on drain current in DE mode of operation.
The device stability analysis has been done with the help of Smith plots. Figure 6(a) shows model and measured s-parameters [29]. Smith plots analysis reveals that proposed device capacitance increases with frequency. At the lowest input frequency the input reflection coefficient, i.e.S11=+1, represents maximum reflection and open circuit. With the rise in frequency the input reflection coefficient moves towards clockwise direction in the circle of capacitance and approaches to the matching point at S 11 =0. Since, at the matching point no reflections would occur because of the impedance matching and this confirms good performance of device at higher frequency range. Similarily output reflection coefficient S22 moves from maximum reflection to minimum reflection towards matching point in the circle of capacitances. Graphs also depicts that with rise in frequency, both the transmission coefficients (S21) and (S12) move towards clockwise direction in the circle of inductances assuring good performance of device at microwave frequency range. The device simulation and measured gains [19], [30] are plotted as a function of frequency at a gate bias of V gs =-1V in Figure 6(b). On comparison the results and found to be within close conformity thus validating device performance in microwave frequency range. Graph clearly demonstrates that the gains decrease with the rise in frequency and the cut-off frequency (f t ) occurs at 68 GHz and maximum oscillation (f max ) occurs at 178GHz. In Figure 7(a), the variation of capacitances i.e. C gd , C gs , C gg and C ds are demonstrated with the rise in frequency. It clealy shown that capacitance values remain almost constant up to 200GHz frequency range that is covering maximum oscillation frequency of device. Figure 7(b) demonstrates the simulated and experimental variation of cutoff frequency with V gs at the V ds =24 V. Figure 8 shows variation of simulated and experimental transconductance with V gs . Comparison of simulation and experimental results [30] validate device suitability for microwave range of frequency. Figure 6. S-parameters (S11, S12, S21 and S22) plot on smith chart, simulated (dashed blue lines) measured (solid red lines) at bias V ds =24V and V gs = -1V, frequency f start =1GHz and f stop =200 GHz (b) Gains versus frequency plot for V ds =24V and V gs = -1V.

CONCLUSION
Finally it can be concluded that the extracted small signal model parameters of dual material gate Al 0.3 Ga 0.7 N /GaN HFET structure are accurate and predict proposed device suitability for LNA that can operate in microwave range of frequencies. Device structure is simulated for analysis of transfer characteristics, output current voltage characteristics and microwave figure of merits. Simulated results are compared with experimental data to analyze device performance and behavior under dc biasing. We obtained maximum oscillation frequency (f max ) of 178 GHz and cut-off frequency (f t ) of 68 GHz as enhanced device features. Important figure of merits analysed and reported in the article include current gain |H 21 |, transducer power gain (G TP ), unilateral transducer power gain (G UTP ), maximum stable gain (G MS ), maximum available gain (G MAX ), transconductance (g m ), drain conductance (g ds ), stern stability factor (k), available power gain (G AP ) and time delay (τ) to assess microwave performance of proposed device. Extracted parameters are validated for consistency and accuracy with experimental results and found to be in close conformity.