IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

Received Dec 20, 2017 Revised Feb 19, 2018 Accepted Mar 9, 2018 The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an external voltage reference nor a current source and able to detect, identify and localize the circuit faults. Hence the BICS requires less area and is more efficient than the conventional current sensors. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. Both bridging and open faults have been analyzed in proposed work by using nwell 0.18μm CMOS technology. Keyword:


INTRODUCTION
Testing of the low-voltage large VLSI circuits is the critical portion of the circuit designing and implementation. Current measurement based testing has been very effective in detecting physical defects such as open, shorts and bridging defects [1], [2]. I DDQ testing is a current-based test method that does not require propagation of a fault effect to an observe output. It requires only exercising the fault circuit and then calculating the current from power supply. The fault is observed by the measurement of current which exceed some threshold limit. The circuit draws a very low current (µA) in the quiescent state but for the certain input state this current may raise to an abnormal level due to the presence of faults [3], [4]. I DDQ test methodologies can be classified into two groups, external (off-chip) and internal (on-chip) I DDQ testing. External I DDQ testing monitors supply current through the power pins of the integrated circuit package while internal I DDQ testing monitors power supply current through the built-in current sensors (BICS). On-chip built-in current sensors are advantageous over off-chip current sensors for detecting the defective quiescent current due to better discrimination and higher testing speeds [5]. Figure 1 shows the block diagram of the I DDQ testing with BICS.
I DDQ testing can be done by adding BICS in series with power supply (VDD) or ground (GND) lines of the circuit under test. A series of input stimuli is applied to the device under test while monitoring the current of the power supply (VDD) or ground (GND) terminals in the quiescent state conditions after the inputs have changed and prior to the next input change. The steady state or quiescent current testing of CMOS integrated circuits is known to be very efficient for improving test quality [6]- [8].
I DDQ testing can be used as a reliability predictor due to its ability to detect defects that do not yet involve faulty circuit behavior, but could be transformed into functional failures at an early stage of circuit life. Thus, I DDQ testing became a powerful complement to the conventional logic testing. Under the fault conditions, the normal values of quiescent current may be increased, decreased or generally distorted. Thus, fault detection can be accomplished by monitoring the quiescent current fluctuations using a current sensing circuit. Any current above the quiescent current would indicate the presence of physical defects in the circuit. In this paper, a simple built-in current sensor (BICS) is presented to detect short (Bridging) and open fault in low voltage two-stage CMOS operational transconductance amplifier with fault injection transistor [9]- [11].
The format of this paper is as follows; two stage operational transconductance amplifiers are discussed in Section 2. Section 3 introduces fault modeling whereas Section 4 describes the design consideration for BICS. Test simulation results and discussion are given in Section 5 and Section 6 contains conclusions.

TWO STAGE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
In high performance analog integrated circuits, operational transconductance amplifier with very high DC gain and high unity gain frequency are needed to meet both accuracy and fast settling requirements of the systems [12]. Therefore, two-stage CMOS OTA are considered ideal for above requirement. Operational transconductance amplifier is voltage controlled current source whose differential input voltage produces an output current. An OTA is basically an operational amplifier (OPAMP) without an output buffer. It can drive only capacitive loads. The OTA can also be defined as an amplifier where all nodes are at low impedance except the input and output nodes. The characteristic feature of an ideal transconductance amplifier is that it has infinite input and output resistances. There is usually an additional input for a current to control the amplifier transconductance. It replaces operational amplifier because of its high bandwidth, high voltage swing, high SNR, low power dissipation, and high input impedance even at low voltages and low power. OTA constitute as a major building block in the analog designing due to its unique characteristic suited for applications such as gain control, multiplexing, comparator, analog modulation, active-c filter, oscillator etc. The OTA is a current-mode circuit and a versatile amplifier which convert input voltage to linearly proportional output differential current with transconductance gain (G m ). At higher frequencies, they provide more reliable performance due to its current mode operation. OTAs provide highly linear tenability of their transconductance (G m ) [13], [14]. In OTA the output current is linear function of differential input voltage as shown in Equation (1).
Where G m is the transconductance gain, I OUT is output current and V in is the input voltage. The basic circuit diagram of two-stage OTA is shown in Figure 2 with differential amplifier and current mirror as first stage which convert differential input to single-ended output. The transistor M6 serves as P-channel common source amplifier which is the second stage of op-amp which provides high voltage swing. IBIAS of the circuit goes through current mirrors formed by P-channel MOSFETS, M8, M5 and M7. The sizes of the transistors are designed for a bias current of 113 µA to provide for sufficient output voltage swing, output-offset voltage, slew rate, and gain-bandwidth product.

Fault injection transistor (FIT)
Fault injection transistor (FIT) basically n-MOS transistor is used for inducing bridging faults in the system to measure the fault tolerance or robustness of the system. The fault in the CUT can be activated by the fault injection transistor. Moreover, the use of a FIT for the fault simulation prevents permanent damage to the CUT by introduction of a physical metal short and also enables the operation of the CUT without any performance degradation in the normal mode. When FIT is inactive, CUT operates in normal mode while CUT work in test mode, when FIT is activated without affecting the overall operation of the circuit.

DESIGN CONSIDERATION OF BICS
In I DDQ testing, the BICS embedded in series with VDD or GND lines of the CUT checks whether the quiescent current is below or above a threshold level. The existence of fault without performance degradation of CUT is indicated by proposed BICS. For effective use of internal testing, the BICS must minimize the effect of capacitance and voltage drop and achieve minimum disturbances in the CUT [17]- [19].
In the present work, a simple design of a BICS is presented to detect short faults and open faults on CMOS OTA as shown in Figure 3. Current mirror circuit is an essential element of the proposed BICS in which the reference current in one branch of the circuit is accurately reproduced in the other branch, in a constant current stage. BICS"s ability to detect abnormal current due to physical defects depends on performance of current mirror. It consists of a current differential amplifier (M12, M13), two current mirror pairs (M11, M12 and M13, M14) and an inverter. The n-MOS current mirror (M11, M12) is used to mirror the current from the constant current source which is used as the reference current IREF for the BICS. The current mirror (M13, M14) is used to mirror the difference current (IDEF-IREF) to the current inverter, which acts as a current comparator. The differential pair (M12, M13) calculates the difference current between the reference current IREF and the defective current IDEF from the CUT.  The CUT works in two modes: the normal mode and the test mode. In the normal mode, the BICS is totally isolated from the CUT so that the operation of CUT is not affected by the BICS. In the test mode, the CUT is connected to the BICS. The Venable signal which is applied to the gate of transistor M9 decides the mode of operation of CUT. During the normal mode, the "VENABLE" signal is at logic "1" and all the IDD current flows to ground through M9 (enable transistor) whereas during the test mode, the "VENABLE" signal is at logic "0", the quiescent current from the CUT is diverted in to the BICS and compared with reference current to detect the presence of the fault. When the quiescent state current is greater than the reference current, the output signal PASS/FAIL is set to 1, which indicates the existence of fault in the circuit. When the quiescent state current is less than the reference current, the output signal PASS/FAIL is set to 0, which indicates the nonexistence of fault [21]- [24].
The built-in current sensor of the present work requires less area and is more efficient than the conventional current sensors. It is shown that with the use of a novel fault injection technique, combined with a built-in current sensor design, has significantly improved the testing of mixed signal integrated circuits.

SIMULATION RESULTS AND DISCUSSION
The fault coverage is achieved by the I DDQ test approach based on the simulated results obtained from PSPICE (Cadence PSPICE A/D Simulator) simulations. SPICE level 7 MOS model parameters used in simulation. The CUT is simulated using 0.18µm n-well CMOS technology. Figure 4 shows the simulated output of CUT without BICS. When CUT is given a pulse signal of 1.5V and 1V peak-to-peak, the output obtained is a pulse wave of 1.8V peak-to-peak. The simulated output response of CUT with BISC when fault are not activated i.e. when fault free circuit with BICS is in normal mode is shown in Figure 5. Since the output of CUT is 1.5V peak-to-peak, we can see that there is no performance degradation of the CUT with BICS. In the present work, seven bridging faults viz., short between gate and drain of M3 transistor (  Figure 6. During the test mode, the "Venable" signal is at logic "0" and fault injected transistor are activated using error signal Ve1, Ve2, Ve3, Ve4, Ve5, Ve6, Ve7 and Ve8 respectively. The value of W/L of FIT is taken as 3.5/0.18. The load capacitance is assumed to be 3pF. The simulated BICS output when the fault XFIT1 is activated with Venable signal low and Ve1 high i.e. when CUT is in test mode is shown in Figure 7. We can see that BICS output PASS/FAIL is at logic "1" during the period when fault XFIT1 is activated and thus the fault XFIT1 is detected. Similarly Figure 8 to Figure 14 shows the simulated BICS outputs when faults XFIT2, XFIT3, XFIT4, XFIT5, XFIT6, XFIT7 and XFIT8 are activated with Venable signal low and Ve2,Ve3, Ve4,Ve5, Ve6, Ve7and Ve8 high respectively. We can observed from the results that except faults XFIT2, XFIT3 and XFIT8, all the other faults have been detected by proposed test methodology providing high fault coverage. From the simulated result, since the output signal PASS/FAIL is 1 only when faults are activated with Venable signal at logic 0, we can observed that the proposed BICS detects the faults. Consequently, we know the proposed BICS detects perfectly a defective circuit.
The average power dissipation, the propagation delay time and transition time are also analyzed to compare the performance of the CUT without BICS and the CUT with BICS. Table 1 lists the simulation results of the power dissipation, propagation delay time and the transition time. The average power dissipation of CUT without BICS and with BICS is 1.1mW and 1.3mW, respectively. Therefore, the average power dissipation overhead is about 15.38% due to the inclusion of the proposed BICS. The low-to highlevel transition time of CUT without BICS and CUT with BICS are 0.5ns and 0.9ns, respectively, while the high-to-low-level transition time without BICS and with BICS are 1.5ns and 1.6ns, respectively whereas 3ns and 3.2 ns respectively are the average propagation delay time of CUT without BICS and with BICS. Therefore, we can conclude from the simulations results that the performance degradation is negligible.    Table 3 summarizes the comparison of the proposed BICS and the previous published BICS. Although a direct comparison cannot be made because the BICS are designed in different technologies, some important results can be drawn from the table. The proposed BICS requires the least devices, i.e., seven transistors and one inverter, among all designs. The BICS does not require any clock signal as well as an external voltage reference or a current source. Hence, the BICS has negligible performance degradation. Furthermore, mode selection is provided which is more economical than other designs. Consequently, it is obvious that this design is competitive with previously proposed BICS"s.

CONCLUSION
In this paper, I DDQ testing technique has been explored on low voltage two stage CMOS operational transconductance amplifier using PSPICE. The proposed BICS design converts the current difference between a faulty current and the reference current to a voltage that differentiates between faulty CUT and fault free circuit. During the normal mode, the bottom of the CUT is connected to ground bypassing the BICS. Therefore, a level shift or disturbance on the output during normal mode of the CUT is avoided. The simulation and test results show that the proposed BICS functions correctly with negligible performance degradation of CUT, requires less area, no external reference source and provides high fault coverage. Hence, the proposed BICS is superior to other BICS"s. Out of eight faults which include seven bridging and one open fault, five faults have been detected by this test methodology. Thus, I DDQ testing methodology is a valuable tool to achieve high fault coverage and also improve reliability and quality of analog and mixedsignal CMOS integrated circuits without incurring significant test development cost. It is concluded that I DDQ testing is very effective in detecting short faults. However, it may not detect an open fault.