A 60 GHz CMOS Power Ampliﬁer for Wireless Communications

This paper presents a 60 GHz power ampliﬁer (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dBm and a peak power added efﬁciency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm 2 .


INTRODUCTION
Wireless communications using the millimeter-wave band have been growing in the past few years due to its high data-rate transmission capability. The demands for high data-rate short range wireless communication have attracted a great deal of interest in the design of 60 GHz systems. As a result, the Federal Communications Commission (FCC) of the United States has officially approved the spectrum utilization for 57 GHz to 64 GHz for commercial use. CMOS PA is among the most challenging building blocks in implementing a 60 GHz system. The main purpose of a PA design is to provide sufficiently high output power, while another important target is to achieve high efficiency. There are several obstacles which make the implementations of a PA very difficult in CMOS technology. The use of submicron CMOS increases the difficulty of implementation due to technology limitations such as low breakdown voltage and poor transconductance. The linearity and power efficiency are lower than other technologies. However, with the trend of lower power transmitters in the next generation, implementation of CMOS PAs with good efficiencies are becoming realistic despite steadily declining field-effect transistor (FET) breakdown voltages.
In this paper, we are going to present the designs and measurement results of a 60 GHz PA targeted for wireless communications. The paper is organized as follows. Section 2 presents fundamentals of power amplifiers. Section 3 introduces the architecture of the proposed 60 GHz PA including a detailed description of the circuit topology. The measurement results are presented in section 4 and conclusions are given in the last section.

POWER AMPLIFIER BASICS 2.1. PA Block Diagram
The general design concept of a PA is given in Fig. 1. The two port network is applied in the design consisting of two matching networks that are used on both sides of the power transistor. Maximum gain will be realized when the matching networks provide a conjugate match between the source/load impedance and the transistor impedances [1]. Specifically, the matching networks transform the input and output impedances Z 0 to the source and π-2π B π C 0-π load impedances Z S and Z L , respectively. Both input and output matching networks are designed for 50 Ω external load. Figure 1. Block diagram of a PA.

Classification of PAs
There are generally two types of PAs: the current source mode PA and the switching mode PA. Different kinds of each mode of PAs and their functional principles are introduced in detail in [2]. In the current source mode PA, the power device is regarded as a current source, which is controlled by the input signal. The most important current source mode PAs are class A, class B, class AB and class C. They differ from each other in the operating point. Fig. 2 illustrates the different classes of the current source mode PA in the transfer characteristic of a FET device. The drain current I D exhibits pinch-off, when the channel is completely closed by the gate-source voltage V GS and reaches the saturation, in which further increase of gate-source voltage results in no further increase in drain current. The other very important concept to define the different classes of the current source mode PA is the conduction angle α. The conduction angle depicts the proportion of the RF cycle for which conduction occurs. The conduction angles of different classes are summarized in table 1.

PA Efficiency
Efficiency is a measure of performance of a PA. The performance of a PA will be better if its efficiency is higher, irrespective of its definition. The PA is the most power-consuming block in a wireless transceiver. Its power 928 ISSN: 2088-8708 efficiency has a direct impact on the battery life of mobile devices. Several definitions of efficiency are commonly used with PAs. Most widely used measures are the drain efficiency and power added efficiency. The drain efficiency is defined as where P OUT is the RF output power at operating frequency and P DC the DC power consumption of the PA output stage. It reveals how efficient the PA is when it converts the power from DC to AC. The PAE is given by where P IN is the input power fed to the PA and P DC the total DC power consumption of the PA. The PAE gets close to η if the gain of the PA is sufficient high so that the input power is negligible.

DESIGN OF 60 GHz POWER AMPLIFIER
The 60 GHz PA is designed using 55 nm CMOS process provided by Fujitsu Ltd. Its back end consists of 11 copper layers and a top aluminum redistribution layer (RDL). The cross-view of a grounded coplanar wave-guide transmission line (GCPW-TL) is depicted in Fig. 3 [3]. The GCPW-TL with the characteristic impedance of 50 Ω (the 50 Ω GCPW-TL) is used for shunt and series stubs of the matching networks and for connecting to the input and output pads of the 60 GHz PA. Its signal line consists of the RDL layer with a width of 8 µm. Ground (GND) walls composed of the 6th to 11th metal layers with a width of 9 µm are placed on the both side of the signal line at the distance of 11.5 µm. The 3rd to 5th metal layers are meshed and stitched together with vias to form the GND plane.  Fig. 4. It includes an input matching network, an output matching network, two common-source based amplifying stages and an interstage matching network. For bandwidth enhancement, multi-stage matchings using capacitors and GCPW-TLs are adopted. The series capacitors and GCPW-TLs form 4th-order and 2nd-order high-pass filters at the input and output of the PA, respectively. The input is matched to 50 Ω for measurement purpose while the load is optimized for maximizing output power using load-pull simulation. The inter-stage matching network is based on the PI network for wideband performance. A 128 Ω resistor is added in series to the transistor's gate of the first amplifying stage for stabilization. The minimum-loss cascade stabilizing resistor value is determined from the Smith chart by finding the constant resistance that is tangent to the appropriate stability circle [4]. All of the capacitors also act as coupling capacitors while the DC bias voltages are applied through the shunt GCPW-TLs. The bias voltages are common to all amplifying stages. The connection between the MOSFETs, MOM capacitors and GCPW-TLs are made by the 10th and 11th metal layers. The lengths of the GCPW-TLs and the MOM capacitor values are determined by a nonmetric optimization process taking into account the models of MOSFETs, MOM capacitors and GCPW-TLs. The parasitic components are extracted using bond-based design which is a measurement-based design approach to avoiding the difficulty associated with layout parasitics when ordinary layout parasitic extraction (LPE) tools used for chip design do not extract inductances [5]. The far end of each shunt stub is terminated by a wideband decoupling power line with very low characteristic impedance (the 0 Ω TL) [6].

MEASUREMENT RESULTS
In order to verify the performance of the 60 GHz PA, a chip prototype was fabricated in 55 nm CMOS. Fig. 5 shows the die microphotograph of the PA. The PA occupies an area of 0.72×0.63 mm 2 including probe pads. The PA was measured by means of on-chip probings using a probe station. The RF probe pads were designed for ground-signal-ground (GSG) probes with 750 µm pitch. The Anritsu 37397D VNA and V-band frequency extenders were used for measuring small-signal S-parameters.   VTXFA-06-12 signal module were used for generating input signal at 60 GHz while a VDI PM5-305V power sensor was used to measure the output power. Due to the equipment limitation at V-band in our laboratory, the output power can only be measured up to -3 dBm of the input power. At 60 GHz, the designed PA obtains a OP1dB of approximately 4 dBm. Fig. 8 and Fig. 9 show the drain efficiency and PAE versus the input powers, respectively. The designed PA archives a peak PAE of 12.6% at -3.5 dBm input power. The PA consumes a total power of 38.3 mW from a 1.2 V supply voltage. Table 2

CONCLUSIONS
In this paper, we have presented the designs and measurement results of the 60 GHz PA targeted for wireless communications. The proposed PA obtains the peak gain of 16 dB while the -3 dB bandwidth cover the entire of the