A New Proposal for OFCC-based Instrumentation Amplifier

Received Sep 14, 2016 Revised Nov 20, 2016 Accepted Dec 5, 2016 This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included. Keyword:


INTRODUCTION
Design and development of analog signal processing and generating circuits using current mode (CM) building blocks has been mainstay for past few years. Current conveyor and its variants, being versatile CM building blocks, have been used extensively for these applications. The operational floating current conveyor (OFCC) [1] is a variant of current conveyor with attractive features of both high and low impedance at input and output ports which make it suitable for sensing both currents and voltage and providing the sensed variable in form of current and voltage. The OFCC has been used to develop variable gain amplifier [1], basic amplifier circuits (voltage, current, transimpedance and transconductance) [2][3][4], filters [5][6][7][8][9][10], instrumentation amplifier [11], [12], readout circuits [13], logarithmic amplifier [14], rectifier [15], and wheatstone bridge [16] in recent past.
The findings are placed in Table 1 and following points are noted: a. The structures presented in [30], [31] use large number of active blocks while those reported in [12 Figure 4(a)], [22][23][24], [27], [39] employ many passive components. b. The input impedance of all VMIAs is high while the output impedance of [11], [32][33][34][35][36], [38][39][40][41] is not appropriate therefore an additional active block would be needed to access the output. c. Though the active block count is less than or equal to three in [32][33][34][35], [38][39][40][41], but an additional active block is needed to access output. d. The VMIA [12 Figure 5(a)] uses three number of active blocks and resistors each and presents output at proper impedance level. e. Both VM and CM active blocks are employed in [29][30][31], [36], [37] therefore the bandwidth is governed by VM block. f. Component matching is needed in [12], [22][23][24], [27][28][29][30][31] for proper operation.  The paper is detailed in four Sections. Section 2 describes OFCC port relationship and proposed OFCC based VMIA topology. This Section also includes the behavior of proposed topology in presence of non-idealities namely finite transimpedance gain and tracking errors. The verification of theoretical predictions is done both through simulations and experimentation. The corresponding results are put forward in Section 3. The findings of the paper are concluded in Section 4.

PROPOSED OFCC BASED VMIA 2.1. Operational Floating Current Conveyor (OFCC)
The OFCC has two inputs and two outputs and is represented by circuit symbol shown in Figure 1. The input ports Y and X (W and Z) is used respectively for sensing (providing) voltage and currents. The ports X and W have low impedance whereas ports Y and Z present high impedance. Ref The OFCC operation is based on the port relationship of (1): Here, the term Z t represents open loop transimpedance and its value is very high, therefore feedback between W and X port is essential for developing any application. The frequency dependence of parameter Z t in (1) is represented using single pole model and is approximated as Z t (s) = 1/sC p at high frequencies where C p = Z to ω tc (Z to represents open loop transimpedance gain and ω tc corresponds to its cut off frequency). The voltage and current transfers at X and Z ports have a multiplication factor of α and β. Ideal values of these factors are unity, however, in practice there is deviation from this value. The effect of non-ideal voltage and current transfers on circuit operation depends strongly on topology e. g. the performance of the circuit remains unaffected if the terminals whose behaviour is affected by nonideal behaviour are not used in case of current terminal or corresponding voltage port is grounded.

Proposed Topology
The architecture of the proposed VMIA, as depicted in Figure 2, comprises of two stages. The first stage, comprises of two OFCCs and a current determining resistor R 1 , provides current proportional to input voltage difference (V in1 -V in2 ). A single OFCC (OFCC 3 ) and a resistor are used in second stage which converts the current output of first stage to voltage. Using the port relationships of (1), voltages at nodes P and Q in Figure 2 are computed as which give current output (I out ) of the first stage as where ( ) .
The third OFCC coverts I out to output voltage (V out ). Routine analysis of the circuit gives V out as where ( ) .
Substituting I out in Equation (5) yields Representing V in1 = V CM + Δ and V in2 = V CM -Δ, differential mode gain (A d ) and common mode gain (A CM ) are computed respectively as: It is clear from Equation (8) that if the OFCCs are matched, the current output (I out ) would be zero for common mode input and would result in zero output voltage. There will be deviation from zero output if the OFCCs at input stage are not matched which are discussed in the following Section. Using Eqs. (7) and (8), the common mode rejection ratio (CMRR) is calculated as In practice, the values of β 1 and β 2 are close to unity, therefore the proposed topology can give a high value of CMRR. Considering α = 1, β 1 =β 2 =1 and frequencies much below ( ( ) ( )), Equation (7) reduces to (10) It is clear from Equation (10) that no matching constraint is imposed on component values for obtaining differential gain. Comparing the proposed VMIA with available OFCC based VMIAs [12 Figure 5(a)] having similar input and output impedances, it is found that later uses equal resistors in first stage.

SIMULATION AND EXPERIMENTAL RESULTS
The proposal is examined through SPICE simulations wherein CMOS based schematic of OFCC of    For validation of simulated observations the proposal is prototyped. The OFCC is realized with commercially available IC AD844AN [42] using the setup shown in Figure 7. Experimental observations are plotted for frequency response and CMRR as shown in Figure 8(a) and Figure 8(b) respectively. Output signal obtained through prototype for input signal at frequency of 100 kHz and 1 MHz is shown in Figure 9(a) and Figure 9(b) respectively for authentication. Figure 10(a) shows practical performance for sinusoidal, Figure 10(b) for square and Figure 10(c) for triangular input signals at frequency of 100 kHz each as a proof of the proposal.

CONCLUSION
An OFCC based VMIA is proposed in this work that uses three OFCCs and two resistors. The input and output impedances of the proposal are high and low respectively therefore the structure can be used to sense signal from voltage sensor and interface output with system processing voltage signal. Effect of non idealities on behavior of proposal is included. Workability of the proposal is verified through SPICE simulations and experimentations. Comparison of the proposed VMIA with its available counterparts shows that it has highest CMRR GBP and has lowest component count.