Single-Stage Quadrature LMVs

Received Mar 10, 2017 Revised Jun 17, 2017 Accepted Jul 1, 2017 This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply. Keyword:


INTRODUCTION
Low power, low-voltage, and highly integrated circuits are always the main topics for integrated circuit design, especially very important for mobile wireless communication systems due to the limitation of battery life. Single stage circuits combining mixer and oscillator have been designed for the purpose of a higher degree of integration and reducing power consumption. For highly integrated low-power receiver front-end, a current reuse technique is typically chosen across different functional blocks. A popular method is cascoding the mixer on top of the input stage of the low-noise amplifier (LNA), while less frequent is stacking mixer and voltage-controlled oscillator (VCO) [1][2][3][4][5]. to the input port of the current source. For the conventional VCO, the down-converted IF signal at the VCO output is negligible due to the low impedance at the low frequency. If a series resonator is employed, the impedance is high at the low frequency and the IF signal can be recovered without any signal loss [6]. As shown in Figure 1(a), the direct conversion architecture generally requires accurate quadrature LO signals which can be generated by several methods such as combining VCO and poly-phase filter, VCO at double frequency followed by flip-flops, and the quadrature VCO (QVCO). The QVCO is the popular topology to achieve low phase noise (PN) using LC-tuned resonator. As shown in Figure 1(b), the direct connection followed by a cross connection of two differential VCOs forces to oscillate in quadrature. There are several QVCO topologies reported. The most common QVCO is called parallel QVCO (P-QVCO) which couples two VCOs in quadrature with parallel coupling transistors. Another method is called S-QVCO which couples two VCOs in a cascode-like way [7]. While the P-QVCO has low phase and amplitude errors, it has rather poor phase noise performance. On the contrary, the S-QVCO exhibits good phase noise performance with good quadrature accuracy. The third method is to couple two VCOs through the body terminals (or back-gate) of the VCO core transistors [8]. The back-gate coupled QVCO (BG-QVCO) has low phase noise compared to P-QVCO and S-QVCO. However, the BG-QVCO has larger phase and amplitude errors compared to P-QVCO and S-QVCO.
In this paper, several quadrature LMVs are proposed combining LNA, mixer, and QVCO. By exploiting a series LC (SLC) network instead of a parallel LC (PLC) network, the low frequency IF or baseband quadrature signal can be directly extracted from the drain outputs of the QVCOs. This paper is organized as follows. In Section II, the traditional LC tank oscillator is described as a mixer, and a detailed analysis for the proposed quadrature LMV (QLMV) is given. In Section III, an experimental performance is given based on simulation using 65 nm CMOS technology. Finally, a conclusion is given.

CIRCUIT DESIGN OF QLMVs
A conventional LC tank oscillator, as shown in Figure 2, performs the mixing process since an RF signal in the VCO bias current is down-converted by the switching transistors. Also, by the same mechanism, the dc current of M cs is up-converted to the LO frequency. The bandpass characteristic of the PLC resonator responds to the fundamental frequency in the current waveform and rejects higher order harmonics with a differential VCO output voltage.
With the complete switching is assumed for the M sw1 and M sw2 , the current at the VCO output port is given by where I CS and g m are the dc current and transconductance of the current source M CS , respectively [9]. The first term in (2) is the LO component of the VCO. The low frequency IF signal (the 2 nd term) is severely attenuated since the inductor of the PLC tank is short at around dc. Also, the high frequency component (the 3 rd term) is attenuated by the PLC tank. Attempting to sense the down-converted component at the VCO  [2]. One possible solution is to exploit the SLC network for the VCO to extract both LO and IF signals [6]. Figure 3(a) shows a SLC VCO where the coupling capacitor C cpl and the inductor 2L form a SLC network. At the LO frequency, Figure 3(a) is a NMOS and PMOS cross coupled complementary VCO. When an RF signal is applied to the input of the transconductance stage, the topology with the resistance and PMOS cross-coupled load is exactly the same as the single-balanced mixer since the coupling capacitor C cpl is open at IF frequency. In Figure 3(a), the current source can be modified as an LNA. The RC low-pass filter attenuates the LO component of the VCO at the drain nodes while somewhat degrading the phase noise performance. The transistor M cs can be modified as an LNA at RF by adding inductors at the gate and the source, while providing the dc bias current to the VCO. Similarly, M sw,n performs the mixing operation while contributing the negative resistance to the VCO. Furthermore, M sw,p adds more negative resistance to the VCO core. As shown in Figure 3(a), RF component is down-converted around dc, and the dc component is up-converted to the LO frequency. Looking at the gate nodes, the IF component at the gate nodes is severely attenuated since the inductor is short at the IF frequency. However, looking at the drain nodes, the IF component appears without attenuation since the C cpl is open at around dc. With just adding the simple RC low-pass filter (LPF), the LO component can be rejected with significant attenuation and leaving the downconverted signal at the IF output. The SB-LMV cell requires only small size capacitance compared to the LMV cell in [2] which requires quite large size capacitance for the same LPF corner frequency since the impedance looking at the source nodes at the IF outputs is quite low. Figure 3(b) shows the equivalent single balanced mixer for the IF frequency. The load resistance is given by

SLC filter
where g mp is the transconductance of the cross coupled PMOS transistor. In (3), it can be seen that the load resistance can be maximized when R L equals 1/g mp . Figure 4 shows the simulated voltage gain with and without the PMOS load. As shown in Figure  4(a), the maximum voltage gain is limited by the resistor load with different bias current since the resistor consumes the voltage headroom. On the contrary, the voltage gain with the cross coupled PMOS load can be significantly enhanced by canceling the load resistance with negative resistance of the PMOS transistor as shown in Figure 4(b) and Figure 4(c).
Also, the noise figure (NF) of the mixer can be improved with the increased gain as shown in Figure 5. The simulation result shows that about 6 dB NF improvement is achieved with the PMOS active load at higher offset frequencies. The single balanced SLC VCO in Figure 3 can be designed to generate quadrature signals while performing the frequency mixing. Figure 6 shows several topologies for quadrature signal generation using two VCOs [7], [8].    Figure 7 based on the QVCO topologies in Figure 6. Each QLMV has the same merits and demerits of each QVCO in Figure 6. The LNA part in Figure 7 is designed by adding a small size extra capacitor between the gate and source of the current source transistor, which enables to apply a power-constrained simultaneous noise input matching (PCSNIM) technique for low-power design [10], [11]. Figure 8 shows the small-signal equivalent circuit of the LNA in Figure 7(d). The noise meansquared gate induced noise current is given by In (4), k is the Boltzmann constant, T is the absolute temperature, δ is a constant with value of 4/3 in long-channel devices, C gs is the gate-source parasitic capacitance of the RF input transistor, g d0 is the drainsource conductance at zero drain-source voltage, and Δf is the bandwidth, respectively. Since the gate induced noise current has a correlation with the drain channel noise current, its correlation coefficient is given by The noise factor (F) and noise parameters (noise resistance R n , optimum noise impedance Z opt , and minimum noise factor F min ) are given by where γ is unity at zero V DS and 2/3 in saturation mode transistor operation with long channel devices, α=g m /g d0 is unity for long channel devices and decreases as the channel length decreases, C t =C gs +C ex , and ω T is the cutoff frequency and is equal to g m /C gs , respectively. The input impedance Z in of the LNA is given by

IFQ-IFQ+
Comparing (9) and (11), the condition that satisfy (12) is given by From (13) and (15), the source degeneration inductor can be approximated by Assuming δ/γ is nearly constant which is about 2, α is less than unity, and |c|=0.395 for the short channel transistors [9].

PERFORMANCE OF THE PROPOSED QLMVs
A symmetric inductor is used to have a higher quality (Q) factor (Q=12.5 at 2.4 GHz) to have a better phase noise performance. The ac coupling capacitor C cpl is implemented with metal-insulator-metal (MIM) capacitor. The tuning range is varied with the MOS varactors. The transistors M cpl and M sw,n in Figure  6 are set to have the same size for fair comparison. The width of the switching transistors is 32 µm with the minimum channel length of 60 nm. The size of C ex , L g and L s are chosen following the PCSNIM technique to match the signal source impedance of 50 ohm. The value of C ex is about 80 fF. Figure 9(a) shows the frequency domain analysis of the LO and IF output of the S-QVCO LMV. Figure 9(b) shows the signal swing at the RF input and IF output when -80 dBm RF input signal is applied. The voltage conversion gain is about 32 dB. Figure 10   As shown in Figure 10(b), the double sideband noise figure (NF DSB ) of the S-QVCO LMV is lower at low offset frequencies less than 0.1 MHz and higher at high offset frequencies larger than 0.1 MHz compared to other two QLMVs. The NF DSB of the S-QVCO is about 9.6 dB at 1 MHz offset frequency. Table  I summarizes the performance of the proposed QLMVs. To simulate the phase and amplitude errors, 0.1% tank inductor mismatch is assumed. Even though the P-QVCO LMV has the lowest phase and amplitude errors, it has inferior phase noise performance since the parallel coupling transistor contributes large phase noise. While the BG-QVCO LMV has good phase noise performance, it has large phase and amplitude errors. The S-QVCO LMV has the lowest phase noise performance and power consumption with moderate phase and amplitude errors. From the simulation results, the proposed QLMVs are expected to be successfully integrated for the direct conversion receiver such as Global Positioning System (GPS), satellite communication receiver [12], medical body area network, and cable TV (CATV) set-top box while consuming low power with just one integrated block.

CONCLUSION
By utilizing a series LC resonator, this paper proposes fully integrated RF front-end QLMVs by merging LNA, single-balanced mixer, and quadrature VCO. The proposed QLMVs are designed and simulated using 65 nm TSMC CMOS technology. The proposed QLMVs can be easily integrated on a chip, and applied for low-power high-performance direct conversion RF front-end receiver.