Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric Double Gate MOSFET

This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage.


Introduction
The study on the reduction of transistor size is the biggest issue in the semiconductor industry. The reduction of transistor size doesn't only have advantages in the economical aspect such as productiveness improvement by the increase of packing density and competitiveness increase by reduction of the unit cost, but also plays a large part of competitiveness increase such as the increase of operation speed and improvement of the device reliability by low power consumption in the technological aspect.
Therefore, major transistor businesses are accelerating the invention of ultrafine transistor to be applied to system semiconductor integrated circuits, as well as to memories. However, in the transistors of the existing CMOSFET structure, there are difficulties in producing sub-10nm transistors, because of problems such as threshold voltage roll-off, subthreshold swing degradation, and the intensification of drain induced barrier lowering. To solve these problems, not only new devices using GNR (Graphene Nanoribbon) [1], but also multiple gate MOSFETs using silicon have been studied.
Multiple gate MOSFET is the structure that is able to reduce the above-mentioned short channel effects by improving the control ability of the carrier through positioning more than 2 gate terminals around the channel which can control the flow of carrier within the channel [2]. It is divided into tri-gate structure such as FinFET structure [3], double gate structure [4], and cylindrical structure [5], according to the methods of positioning the gate terminals around the channel. It is known that the structures are different but the basic operations are same. The study will be done about double gate (DG) MOSFET, the simplest structure among them.
DGMOSFET is the structure that makes gate terminals in top and bottom. There are symmetric DGMOSFET which has the same top/bottom structures, and asymmetric DGMOSFET which is produced for controlling short channel effects more efficiently by making top and bottom gate oxide structures different. Although the asymmetric DGMOSFET is the device developed for deducing short channel effects, the short channel effects by tunneling current cannot become ignored in case of reducing the channel length to sub-10nm. Therefore, For this, the model of Ding et al. [6] who induced a series form of hermeneutic potential distribution model from Poisson's equation was used, and WKB (Wentzel-Kramers-Brillouin) approximation was used for inducing the tunneling current model.
In section 2, the tunneling current model, which was calculated using potential distribution induced basically by Ding's model and WKB approximation, will be explained. Section 3 will analyze threshold voltage roll-off according to the changes of oxide and silicon thickness using induced current model, and the conclusion will be made in section 4. Figure 1 shows the schematic sectional diagram of asymmetric DGMOSFT including the relations of tunneling current ( ) and thermionic emission current ( ) to potential energy. As shown in Figure 1, off-current is composed of thermionic emission current and tunneling current, and the flow of the carrier in the channel will be controlled by gate voltage. Especially, the factor to affect the flow of the carrier is the oxide capacitance which changes according to the oxide thickness of top and bottom gates. Because silicon dioxide is generally used as oxide film and the permittivity is fixed, the biggest factor to affect the oxide capacitance is the oxide thickness. Therefore, threshold voltage roll-off will be observed by watching the carrier flow which is changing according to the oxide thickness. For this, potential distribution is calculated using Poisson's equation at first. Different from already published papers [7,8], constant charge distribution was used. This is because the charge distribution can be ignored due to the very small number of charges inside the channel in sub-10 nm DGMOSFET. In case that potential distribution model using constant doping distribution is used, Poisson's equation is represented as following.

Current Model of Asymmetric Dgmosfet
(1) Here, is the permittivity of silicon, and is the concentration of channel doping. The solving process of equation (1), thermionic emission current, and tunneling current model were already represented in previously published papers [9,10]. Total off-currents are as following.
(2) In case that the value calculated in equation (2) is , top gate voltage is defined as threshold voltage [11]. Afterwards, threshold voltage roll-off will be calculated by using the oxide thickness of top/bottom gate and silicon thickness as parameters, and the effect of structural parameters on threshold voltage will be considered.

Threshold Voltage Roll-off of Asymmetric Dgmosfet
In order to demonstrate the validity of the model explained in section 2, 2D simulation results [12] were compared with the results of this paper in Figure 2. Because the case of =4.6 V resulting from being calculated with a parameter of the work function of gate material is consistent with 2D simulation result as shown in Figure 2, this study will analyze threshold voltage roll-off using =4.6 V. In addition, even though the complicated Gaussian distribution function was not used like in the previously published papers [7,8], threshold voltage roll-off was consistent well as the result of comparison. So threshold voltage roll-off will be considered by equation (2) using the potential distribution model of this study and threshold voltage defined in TCAD. Firstly, the result of calculating threshold voltage roll-off according to the change of bottom gate oxide thickness was shown in Figure 3 under the given condition. It was found that threshold voltage roll-off changed into approximately -0.52~-0.28 V according to bottom gate oxide thickness, as the result of calculating off-current including tunneling voltage when the thickness of top gate oxide and silicon was fixed at 1.5nm and the channel length was changed from 10 nm to 5nm. However, in the case of not including tunneling current, threshold voltage roll-off was -0.28 V~-0.12 V, which shows a sensible difference.
Especially as channel length gets shorter, the change of threshold voltage roll-off according to the change of oxide thickness appears more greatly. As the channel length decreases, the threshold voltage roll-off due to the tunneling effect is further exacerbated. Moreover, as channel length gets shorter, oxide thickness influences threshold voltage roll-off more sensitively. Even when parameters of top/bottom oxide thickness were exchanged mutually, the same result was induced. As Figure 3 shows, it can be found that threshold voltage roll-off increases if bottom oxide thickness increases. Therefore, in order to decrease threshold voltage roll-off, oxide thickness should be made as thin as possible during the manufacturing process. Like the above, because tunneling current cannot ignore in condition of sub-10nm, from now on, only threshold voltage roll-off including tunneling current will be considered. Short channel effects occur according to silicon thickness making up channel, as well as channel length. To observe this effect, after top/bottom oxide thickness was fixed at 1.5nm, threshold voltage roll-off including tunneling current was illustrated in Figure 4 with silicon thickness changing from 1 to 4 nm. As shown in Figure 4, it can be observed that threshold voltage roll-off decreased greatly in case that silicon thickness decreased. It can be observed in the Figure 4 that when channel length decreased from 10nm into 5nm, threshold voltage roll-off was approximately -0.3 V in 1 nm of silicon thickness and increased to -1.9 V in case that silicon thickness increased to 4nm. That is, as silicon thickness increased, short channel effects appeared greatly. As shown in Figure 4, it is comprehensible that threshold voltage roll-off, in case of channel length decreasing from 10 nm into 5 nm, increased nearly twice if silicon thickness increased by 1 nm. If Figures 3 and 4 were compared, it can be found that not oxide thickness but the change of silicon thickness affects threshold voltage roll-off more greatly. Like the above, because threshold voltage roll-off is great if silicon thickness increases to 4nm in sub-10 nm DGMOSFET, silicon thickness in designing DGMOSFET should be as thin as possible in production process. In order to observe the effect of silicon thickness and oxide thickness on the threshold voltage roll-off in detail, Figure 5 shows the contour plot of the tunneling current and the  Figure 5, the thermionic current is dominant over the tunneling current when the channel length is near 10 nm. However, when the channel length is reduced to 5 nm, the tunneling current increases with the increase of the total drain current. The increase in the tunneling current greatly reduces the threshold voltage, which significantly increases the threshold voltage roll-off. Comparing with the variations of the tunneling current with respect to the change of the silicon thickness and the oxide film thickness in Figure 5(a), it can be found that silicon thickness variation has a greater impact on threshold voltage roll-off than oxide thickness variation. Figure 5. Contours of (a) tunneling current and (b) thermionic current for silicon thickness and channel length with top gate oxide thickness as a parameter.
As considered in Figures 3 and 4, channel length and silicon thickness affect threshold voltage roll-off greatly. To consider the effect of channel length and silicon thickness on threshold voltage roll-off more closely, threshold voltage is illustrated in Figure 6 in the condition that bottom gate oxide thickness is given as parameter. As shown in Figure 6, as the silicon thickness increases, threshold voltage decreases greatly. Also, it can be found that as the channel length gets shorter, threshold voltage roll-off occurs very seriously. Especially, if channel length gets shorter, threshold voltage roll-off according to bottom gate oxide thickness occurs more remarkably. As mentioned in Figure 3, it can be found that as bottom gate oxide thickness gets thinner, threshold voltage roll-off decreases, and as bottom gate oxide thickness gets thicker, threshold voltage roll-off increases. In case that channel length is very short like nearly 7 nm, minus threshold voltage is indicated over 3 nm of silicon thickness according to bottom gate oxide thickness. However, it can be comprehensible in Figure 6 that minus threshold voltage appears even over 5 nm of silicon thickness if channel length gets longer by 10 nm. Because operation of DGMOSFET is changed into enhancement mode or depletion mode if threshold voltage is changed into minus and plus, the design should be made very carefully. Because such phenomenon occurs greatly in particular as oxide thickness increases, it is needed that oxide thickness is produced to be thin.
The ranges of channel length and silicon thickness for sub-10 nm DGMOSFET to have 0.3 V of acceptable threshold voltage are indicated in Figure 7, in the ranges of top/bottom gate oxide thickness between 0.5 nm and 2 nm. As mentioned in the consideration of Figure 3, it can be observed in Figure 7 that the result was consistent even though top/bottom gate oxide thickness was switched into each other. That is, it can be found that top and bottom gate oxide thickness for maintaining consistent threshold voltage is in inverse proportion. As shown in Figure 7(a), DGMOSFET with 0.3V of threshold voltage can be designed only when top/bottom gate oxide thickness should be sub-0.5 nm in case of sub-6 nm of channel length. However, because producing sub-0.5 nm of silicon dioxide film can bring difficulties in the process, the research and the process development of new oxide film should be made. Figure 7(b) is the contours to silicon thickness that threshold voltage in the change of top/bottom gate oxide thickness of simulation range under the given conditions satisfies 0.3V. As it can be also known in Figure 7

Conclusion
This paper analyzed the effect of tunneling current on threshold voltage roll-off according to the change of structural parameters, such as oxide thickness and silicon thickness of sub-10 nm asymmetric DGMOSFET. For analyzing this, a series form of hermeneutic potential distribution from Poisson's equation was calculated, and thermionic emission current was calculated by using this potential distribution and tunneling current was obtained by WKB approximation. To compare with a complex numerical method, the threshold voltage shift was analyzed using a simple analytical method. As a result, the analytical model of this paper was in good agreement with the two-dimensional numerical method. Potential distribution in channel affected by top/bottom gate capacitance has an effect on thermionic emission current and tunneling current, and will affect off-current in the end. Therefore, top and bottom gate oxide thicknesses greatly influence on short channel effects generated by off-current.
This paper observed what effect the oxide thickness and silicon thickness among short channel effects have on threshold voltage roll-off. As a result, because threshold voltage roll-off increased very excessively in case that tunneling current was included in off-current, tunneling current must be included in current characteristics of sub-10 nm DGMOSFET. It can be known that threshold voltage roll-off increases as top or bottom gate oxide thickness increases.
In the range of top/bottom gate oxide thickness used in simulation, the change of silicon thickness had more effects on threshold voltage roll-off than that of channel length. In addition, for maintaining threshold voltage consistently, top and bottom gate oxide thickness had to be a relation of inverse proportion to each other. Such result will be a basic technology to lead the miniaturization of asymmetric DGMOSFET, and, furthermore, will make a contribution to the operational improvement of integrated circuit.