Conference paper Open Access

FULLY PIPELINED ITERATION UNROLLED DECODERS - THE ROAD TO TB/S TURBO DECODING

Weithoffer, S.; Klaimi, R.; Nour, C.; Wehn, N.; Douillard, C.


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  <identifier identifierType="DOI">10.5281/zenodo.3971713</identifier>
  <creators>
    <creator>
      <creatorName>Weithoffer, S.</creatorName>
      <givenName>S.</givenName>
      <familyName>Weithoffer</familyName>
      <affiliation>IMT Atlantique</affiliation>
    </creator>
    <creator>
      <creatorName>Klaimi, R.</creatorName>
      <givenName>R.</givenName>
      <familyName>Klaimi</familyName>
      <affiliation>IMT Atlantique</affiliation>
    </creator>
    <creator>
      <creatorName>Nour, C.</creatorName>
      <givenName>C.</givenName>
      <familyName>Nour</familyName>
      <affiliation>IMT Atlantique</affiliation>
    </creator>
    <creator>
      <creatorName>Wehn, N.</creatorName>
      <givenName>N.</givenName>
      <familyName>Wehn</familyName>
      <affiliation>Technical University Kaiserslautern</affiliation>
    </creator>
    <creator>
      <creatorName>Douillard, C.</creatorName>
      <givenName>C.</givenName>
      <familyName>Douillard</familyName>
      <affiliation>IMT Atlantique</affiliation>
    </creator>
  </creators>
  <titles>
    <title>FULLY PIPELINED ITERATION UNROLLED DECODERS - THE ROAD TO TB/S TURBO DECODING</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2020</publicationYear>
  <subjects>
    <subject>Beyond 5G</subject>
    <subject>Turbo Decoding</subject>
    <subject>High-Throughput</subject>
    <subject>Hardware Architecture</subject>
  </subjects>
  <dates>
    <date dateType="Issued">2020-08-04</date>
  </dates>
  <language>en</language>
  <resourceType resourceTypeGeneral="Text">Conference paper</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/3971713</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsVersionOf">10.5281/zenodo.3971712</relatedIdentifier>
    <relatedIdentifier relatedIdentifierType="URL" relationType="IsPartOf">https://zenodo.org/communities/epic_h2020</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by/4.0/legalcode">Creative Commons Attribution 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;Turbo codes are a well-known code class used for example in the LTE mobile communications standard. They provide built-in rate flexibility and a low-complexity and fast encoding. However, the serial nature of their decoding algorithm makes high-throughput hardware implementations difficult. In this paper, we present recent findings on the implementation of ultra-high throughput Turbo decoders. We illustrate how functional parallelization at the iteration level can achieve a throughput of several hundred Gb/s in 28 nm technology. Our results show that, by spatially parallelizing the half-iteration stages of fully pipelined iteration unrolled decoders into X-windows of size 32, an area reduction of 40% can be achieved. We further evaluate the area savings through further reduction of the X-window size. Lastly, we show how the area complexity and the throughput of the fully pipelined iteration unrolled architecture scale to larger frame sizes. We consider the same target bit error rate performance for all frame sizes and highlight the direct correlation to area consumption.&lt;/p&gt;</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/760150/">760150</awardNumber>
      <awardTitle>Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding</awardTitle>
    </fundingReference>
  </fundingReferences>
</resource>
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