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Conference paper Open Access

# A Lightweight Implementation of NTRUEncrypt for 8-bit AVR Microcontrollers

Cheng, H.; Großschädl, J.; Rønne, P.; Ryan, P.

### Citation Style Language JSON Export

{
"publisher": "Zenodo",
"DOI": "10.5281/zenodo.3947856",
"language": "eng",
"title": "A Lightweight Implementation of NTRUEncrypt for 8-bit AVR Microcontrollers",
"issued": {
"date-parts": [
[
2020,
7,
16
]
]
},
"abstract": "<p>Introduced in 1996, NTRUEncrypt is not only one of the earliest but also one of the most scrutinized lattice-based cryptosystems and a serious contender in NIST&rsquo;s ongoing Post-Quantum Cryptography (PQC) standardization project. An important criterion for the assessment of candidates is their computational cost in various hardware and software environments. This paper contributes to the evaluation of NTRUEncrypt on the ATmega class of AVR microcontrollers, which belongs to the most popular 8-bit platforms in the embedded domain. More concretely, we present AvrNtru, a carefully-optimized implementation of NTRUEncrypt that we developed from scratch with the goal of achieving high performance and resistance to timing attacks. AvrNtru complies with version 3.3 of the EESS#1 specification and supports recent product-form parameter sets like ees443ep1, ees587ep1, and ees743ep1. A full encryption operation (including mask generation and blindingpolynomial generation) using the ees443ep1 parameters takes 834,272 clock cycles on an ATmega1281 microcontroller; the decryption is slightly more costly and has an execution time of 1,061,683 cycles. When choosing the ees743ep1 parameters to achieve a 256-bit security level, 1,539,829 clock cycles are cost for encryption and 2,103,228 clock cycles for decryption. We achieved these results thanks to a novel hybrid technique for multiplication in truncated polynomial rings where one of the operands is a sparse ternary polynomial in product form. Our hybrid technique is inspired by Gura et al&rsquo;s hybrid method for multiple-precision integer multiplication (CHES 2004) and takes advantage of the large register file of the AVR architecture to minimize the number of load instructions. A constant-time multiplication in the ring specified by the ees443ep1 parameters requires only 210,827 cycles, which sets a new speed record for the arithmetic component of a lattice-based cryptosystem on an 8-bit microcontroller.</p>",
"author": [
{
"family": "Cheng, H."
},
{
"family": "Gro\u00dfsch\u00e4dl, J."
},
{
"family": "R\u00f8nne, P."
},
{
"family": "Ryan, P."
}
],
"id": "3947856",
"event-place": "University of California, Santa Barbara",
"type": "paper-conference",
"event": "Second PQC Standardization Conference"
}
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