Testability of Switching Lattices in the Stuck at Fault Model

Switching lattices are two-dimensional arrays of four-terminal switches proposed in a seminal paper by Akers in 1972 to implement Boolean functions. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, synthesis methods targeting lattices of multi-terminal switches have found a renewed interest. In this paper, the testability under the stuck-at-fault model (SAFM) of switching lattices is analyzed, and properties of fully testable lattices are identified and discussed. Experimental results are given to analyze the testability of lattices synthesized with different methods.


I. INTRODUCTION
A switching lattice is a two-dimensional lattice of fourterminal switches linked to the four neighbors of a lattice cell, so that these are either all connected, or disconnected. A Boolean function can be implemented by a lattice associating each four-terminal switch to a Boolean literal, so that if the literal takes the value 1 the corresponding switch is ON and connected to its four neighbors, otherwise it is not connected. The function evaluates to 1 if and only if there exists a connected path between two opposing edges of the lattice, e.g., the top and the bottom edges (see Figure 1 for an example). The synthesis problem on a lattice consists in finding an assignment of literals to switches in order to implement a given target function with a lattice of minimal size.
The idea of using regular two-dimensional arrays of switches to implement Boolean functions dates back to a seminal paper by Akers in 1972 [2], but has found a renewed interest recently, thanks to the development of a variety of nanoscale technologies. Synthesis algorithms targeting lattices of multi-terminal switches have been designed [3], [5], [13], [14], and methods based on function decomposition techniques have been exploited to mitigate the cost of implementing switching lattices [8], [9], [10]. Moreover, several studies on fault tolerance for nano-crossbar arrays have been published recently [4], [15], [16], [17].
Besides synthesis and fault tolerance, testability is a major aspect of the design process. While detailed studies on testability have been performed for standard two-level and three-level networks (see for instance [1], [6], [7], [11], [12], [18]), to the best of our knowledge, the testability of switching lattices has not been considered so far. Therefore, in this paper, we study redundancies of lattices under a static fault model: the stuck-at-fault model (SAFM). In particular, we prove that under the SAFM, switching lattices minimized with respect to the number of literals controlling the switches are free of redundancies by construction. Whereas, it can be shown by counter examples that lattices minimized with respect to the number of switches, i.e. minimized with respect to the size, are not in general fully testable. We also identify the properties that make a switching lattice fully testable in the SAFM, and show how these properties resemble the properties that guarantee the full testability of the SOP forms in the SAFM, i.e., the primality of the products and the irredundancy of the cover. Finally, we propose a method for identifying redundant cells in a lattice. We conclude the paper reporting experimental results regarding the testability of lattices synthesized with two different methods [5], [13].
The paper is organized as follows. Preliminaries on the standard stuck-at faults model and on switching lattices are reviewed in Section II. Section III introduces definitions and properties of lattices useful for the analysis of testability, that is then presented in Section IV. Section V describes the strategies for identifying redundant cells in a lattice. Finally, Section VI provides some experimental results and Section VII concludes the paper.

A. Fault Models (FMs)
The standard stuck-at faults model (shortly, SAFM) is wellknown and used throughout the industry for many years [1], [11]. In SAFM it is assumed that a defect causes a basic cell input or output to be fixed to either 0 or 1, i.e., signal lines can assume constant values independent of the inputs.
In the following we simply speak of stuck-at-0 (SA0) and stuck-at-1 (SA1) faults. Now, let C be any combinational logic circuit over a fixed library.
Definition 2: An input t to C is a test for a fault f , iff the primary output values of C on applying t in presence of f are different from the output values of C in the fault free case.
A fault is testable, iff there exists a test for this fault. The goal of any test pattern generation process is a complete test set for the circuit under test, i.e., a test set that contains a test for each testable fault. The construction of complete test sets requires the determination of the faults which are not testable (= redundant), even though it is easy to see that in general the detection of redundancies is coNP-complete. Redundancies have further unpleasant properties: they may invalidate the completeness of the test set and often correspond to locations of the circuit where area is wasted [11]. For this, synthesis procedures which result in non-redundant circuits are desirable. A node v in C is called fully testable, if there does not exist a redundant fault with fault location v. If all nodes in C are fully testable, then C is called fully testable.
Finally, we recall that the investigations with respect to the SAFM are usually based on the single fault assumption, i.e., one assumes that there is at most one fault in the circuit.

B. Switching Lattices
A switching lattice is a two-dimensional array of fourterminal switches linked to the four neightbours of a lattice cell, so that these are either all connected (when the switch is ON), or disconnected (when the switch is OFF). A Boolean function can be implemented by a lattice in terms of connectivity across it: • each four-terminal switch is controlled by a literal; • each switch may be also labelled with the constant 0, or 1; • if the literal takes the value 1, the corresponding switch is connected to its four neightbours, else it is not connected; • the function evaluates to 1 if and only if there exists a connected path between two opposing edges of the lattice, e.g., the top and the bottom edges; • input assignments that leave the edges unconnected correspond to output 0. For instance, the 3 × 3 network of switches in Figure 1 (a) corresponds to the lattice form depicted in Figure 1 (b), which implements the function f = x 1 x 2 x 3 + x 1 x 2 + x 2 x 3 . If we assign the values 1, 1, 0 to the variables x 1 , x 2 , x 3 , respectively, we obtain paths of gray square connecting the top and the bottom edges of the lattices (Figure 1 (c)), indeed on this assignment f evaluates to 1. On the contrary, the assignment x 1 = 0, x 2 = 0, x 3 = 1, on which f evaluates to 0, does not produce any path from the top to the bottom edge ( Figure 1 (d)).
The synthesis problem on a lattice consists in finding an assignment of literals to switches in order to implement a given target function with a lattice of minimal size. The size is measured in terms of the number of switches in the lattice.
A switching lattice can similarly be equipped with left edge to right edge connectivity, so that a single lattice can implement two different functions. This fact is exploited in [5] where the authors propose a synthesis method for switching lattices simultaneously implementing a function f according to the connectivity between the top and the bottom plates, and its dual function 1 f D according to the connectivity between the left and the right plates. In [13], the authors have proposed a different approach to the synthesis of minimal-sized lattices, which is formulated as a satisfiability problem in quantified Boolean logic and solved by quantified Boolean formula solvers. This method uses the previous algorithm to find an upper bound on the dimensions of the lattice. It then searches for successively better implementations until either an optimal solution is found, or a preset time limit has been exhausted. 1 The dual of a Boolean function f depending on n binary variables is the A four terminal switching network implementing the function f = x1x2x3 +x1x2 +x2x3 (a); its corresponding lattice form (b); the lattice evaluated on the assignments 1,1,0 (c) and 0, 0, 1 (d), with grey and white squares representing ON and OFF switches, respectively.
Experimental results show how this alternative method can decrease lattice sizes considerably. In this approach the use of fixed inputs (i.e., constant values 0 and 1) is allowed.

III. LATTICES: DEFINITIONS AND PROPERTIES
In this section we introduce some definitions and present some properties of switching lattices that will be exploited in Section IV for the analysis of their testability.
Let the first row of a lattice be the top row, the last row be the bottom row, and any other row be an internal row. Two cells in a lattice are adjacent if they are in the same column and in two adjacent rows or in the same row and in two adjacent columns. Hereafter, in a lattice we denote path any list l 1 , l 2 , . . . , l m−1 , l m of literals such that l i and l i+1 (for all 1 ≤ i < m) are contained in adjacent cells and: 1) l 1 is contained in a cell in the top row, 2) l m is contained in a cell in the bottom row, and 3) all the other literals (i.e., l 2 , . . . , l m−1 ) are contained in cells of the internal rows. Note that paths in lattices may contain more occurrences of the same literal.
Definition 3: A path in a lattice is unsatisfiable (resp., satisfiable) if contains (resp., does not contain) both a variable x and its complement x.

Definition 4:
The product associated to a satisfiable path is the conjunction of all literals of the path, without repetitions. The product associated to an unsatisfiable path is 0.
For example, in the lattice in Figure 1 (b) the path x 2 , x 1 , x 2 is satisfiable and the path x 1 , x 2 , x 1 , x 2 is unsatisfiable. The associated products are x 1 x 2 and 0, respectively.
With a slight abuse of notation, we consider the products associated to all paths in a lattice L as implicants of the function f L implemented by L. Indeed, f L evaluates to 1 on the set of minterms covered by these products. In this framework, the set of minterms covered by an implicant can be empty: this happens whenever a path is unsatisfiable, as, in this case, the associated product evaluates to 0.
Definition 5: An accepting path for a minterm v in a lattice is a satisfiable path whose associated product covers v.
We now introduce the concept of primality of a path in a lattice which is strictly related to the concept of prime implicant in a SOP: , if the product associated to the sequence of literals obtained removing l i from the path is not an implicant of the function implemented by L. The primality of a path with respect to a literal l implies that: (1) the path cannot contain other occurrences of l, since the corresponding product would not change if we remove one occurrence of l from the path, leaving the others; (2) the path cannot contain pairs x, x, with x = l, since the removal of l would leave the associated product unchanged, and equal to 0; (3) the path might contain cells associated to l (in this case the path is unsatisfiable, and becomes satisfiable after the removal of l). For instance, in the lattice in Figure 1 as the removal of one occurrence of x 2 leaves the associated product the removal of any of its literal leaves the associated product unchanged, and equal to 0.
We finally focus on the single cells in a lattice, and we introduce a property that can be associated to the irredundancy of a SOP. Let c be a cell in a switching lattice L that implements a function f L .
Definition 7: The cell c is essential in L if there exists at least a minterm v in the on-set of f L whose accepting paths always contain c. For instance, in the lattice in Figure 1 (b) all cells on the leftmost column are essential, as they form the only accepting path for the on-set minterm 000; while the top-left cell c in the lattice in Figure 2 (b) is not essential, since for any on-set minterm of the function implemented by the lattice there exists an accepting path that does not include c.
Observe that setting to the constant value 0 a literal in a cell c is equivalent to removing all paths that include c from the lattice L: indeed, the 0 in c disconnects, i.e., makes unsatisfiable, all paths going through c. If, in addition, the cell c is essential for a minterm v, then all accepting paths for v are removed from L. Thus, the function implemented by the lattice changes, at least on v. In this sense, we can associate the notion of essential cell to that of irredundant product: if we remove an irredundant product from a SOP, the function represented by the expression changes, and if we remove from the lattice L all paths that include an essential cell, the function implemented by L changes.
We conclude this section with the following two propositions that characterize how the function implemented by a lattice may change setting one cell to a constant value, i.e., forcing a stuck-at-fault in the cell. Let L be a switching lattice, and let f L be the function implemented by L. Now, consider the lattice L c ←1 obtained replacing a literal in a cell c of L with the constant 1.
Proposition 1: The on-set of the function f L c←1 implemented by L c ←1 is a superset of the on-set of f L , i.e., f on L ⊆ f on L c←1 . Proof: We show that any satisfiable path in L remains satisfiable in L c ←1 . Let p = l 1 , l 2 , . . . , l m−1 , l m be a satisfiable path in L. If this path does not include the cell c, than the corresponding path in L c ←1 is composed by exactly the same literals of p, and is satisfiable. If p includes the cell c, than the corresponding path in L c ←1 is obtained replacing one of the literals of p with the constant 1, and thus it is satisfiable.
Consider now the lattice L c ←0 obtained replacing a literal in a cell c of L with the constant 0. We have: Proposition 2: The on-set of the function f L c←0 implemented by L c ←0 is a subset of the on-set of f L , i.e., f on L c←0 ⊆ f on L .
Proof: We show that any satisfiable path in L c ←0 is satisfiable in L. Let p = l 1 , l 2 , . . . , l m−1 , l m be a satisfiable path in L c ←0 . The thesis immediately follows since the satisfiable path p cannot include the cell c (that has value 0), thus the corresponding path in L is composed by exactly the same literals of p, and is satisfiable.

IV. TESTABILITY IN THE SAFM
In this section we analyze the properties that make a switching lattice fully testable in the SAFM. As we will see, these properties resemble the two properties that guarantee the full testability of the SOP forms in the SAFM: the primality of the products, that ensures the testability of AND gates, and the irredundancy of the cover, that guarantees the testability of the OR gate. In our analysis we will consider stuck-at-faults at the literals that control the four-terminal switches in the lattice. We first introduce the notion of irredundant literal in a lattice.
Definition 8: A literal in a lattice's switch is 0-irredundant (resp., 1-irredundant) if it cannot be substituted by the constant 0 (resp., 1) without changing the function computed by the lattice. For instance, the literal x 1 in the top-left cell of the lattice in Figure 2  The notion of irredundancy can be extended to the whole lattice as follows: Definition 9: A lattice is 0-irredundant (resp., 1irredundant) if any literal contained in it is 0-irredundant (resp., 1-irredundant).
Observe that 0-irredundant literals guarantee the testability of SA0 faults in the corresponding cell of the lattice, while 1-irredundant literals guarantee the testability of SA1 faults. Indeed, since the function implemented by the lattice changes if we set a literal in a cell c to the constant 1 or to the constant 0, the fault in c can be tested on the minterm on which the function changes. Thus, we have We now investigate the relations between minimality of a switching lattice and full testability in the SAFM. We first consider the minimality with respect to the number of switches, i.e., the area of the lattice. Under the SAFM, it can be shown by counter examples that a lattice of minimum size for a given target function is not in general fully testable. Consider for instance the lattice in Figure 2 (a) that implements the function f = x 1 x 2 x 3 +x 1 x 4 : this lattice is of minimum size, but it is not fully testable, because it is not 1-irredundant. On the contrary, lattices minimized with respect to the number of literals in the switches are free of redundancies.
Theorem 1: A switching lattice L with a minimum number of literals is fully testable in the SAFM.
Proof: Suppose that L is not fully testable. This means that there exists at least one redundant cell in the lattice whose literal can be replaced by a constant value, 0 or 1, without changing the implemented function. If replace the literal in this cell with a constant value, we get a new lattice for the same function, with a smaller number of literals, in contradiction with the minimality of the number of literals in L. Figure 2 (d) contains a minimum number of literals (4) and is therefore fully testable.

The lattice in
Note that the minimality of the number of literals is not necessary for the full testability. For example, the lattice in Figure 2 (c) is fully testable, but not minimum with respect to the number of literals, as it contains 5 literals instead of 4.
Finally, we prove in the following theorems that the structural properties of switching lattices that guarantee their full testability in the SAFM are the primality of the paths (for the stuck-at-1 faults) and the essentiality of the cells (for the stuck-at-0 faults).
Theorem 2: A SA1 in a lattice cell c with literal l is testable if and only if there exists a path p that contains the cell c and is prime with respect to l.
Proof: Let L be a switching lattice, and let f L be the function implemented by L.
(If part). Consider a path p in L that contains the cell c and is prime w.r.t. l. Recall that the primality of p w.r.t. l implies that p cannot contain other occurrences of l, p might contain cells associated to l, and p cannot contain pairs x, x, with x = l. We must show that the SA1 in c can be propagated to the output of the lattice L in order to be tested, i.e., we must prove that the function implemented by the faulty lattice differs from the original function f L on at least one minterm. This immediately follows from the primality of the path p. Indeed, if we substitute with the constant 1 the unique occurrence of l in p, the resulting product, which cannot be empty because of the properties of prime paths (see Section III), is not an implicant of f L . Therefore, there exists at least one minterm in the offset of f L covered by this new product. On this minterm the faulty lattice computes 1, instead of 0, since the path p, with l replaced by 1, becomes an accepting path.
(Only-if part). Now suppose that the SA1 in the cell c, with literal l, is testable. As we are injecting a constant value 1 into the lattice, we know, by Proposition 1, that the faulty lattice is always correct on the on-set of f L . Thus, the testability of the SA1 implies the existence of an off-set minterm v of f L on which the faulty lattice computes 1, while the original lattice computes 0. Since whenever the literal l gets the value 1, correct and faulty lattices are identical and have the same behaviour, l must be 0 on v. Let us now denote with p an accepting path for v in the faulty lattice. p is satisfiable and contains the cell c with the constant 1, while it cannot contain cells with literal l since l is 0 on v. Consider the corresponding path q in the original lattice L. p and q are identical in all cells but c, which is labelled by 1 in p and by l in q. The product of all literals in q is an implicant of f L , possibly empty if it contains l. If we remove l, the resulting product is not an implicant since it covers the off-set minterm v. Therefore path q is prime w.r.t. l.
Theorem 3: A SA0 in a lattice cell c is testable if and only the cell c is essential.
Proof: Let L be a switching lattice, and let f L be the function implemented by L. (If part). We show that the function implemented by the lattice with a SA0 in the essential cell c differs from f L on at least one minterm. As we are injecting the value 0 into one cell of L, Proposition 2 implies that the faulty lattice is always correct on the off-set of f L . Thus, to prove the testability of the SA0, we must show that there is an on-set minterm of f L on which the faulty lattice computes 0, while the original lattice computes 1. Let l be the literal associated to cell c. Since c is essential, there exists an on-set minterm v for which all accepting paths include c. On all these paths, l must be 1. Now, if we substitute with the constant 0 the literal l in c, we disconnect all paths going through c, and in particular all accepting paths for v. This the faulty lattice computes 0 instead of 1 on v, and the fault can be tested. (Only-if part). We prove by contraposition that if c is not essential, then a SA0 in c cannot be tested. So, suppose that cell c, with literal l is not essential. By Proposition 2, we know that the faulty lattice, with a SA0 in c, is always correct on the off-set of f L . Thus, it is enough to show that the faulty lattice is correct also on the on-set of f L . Let v be an on-set minterm of f L . Since c is not essential, there exists an accepting path p for v that does not include c. Thus, the SA0 in c has no effect on p, and the faulty lattice correctly computes 1 on v.
V. ALGORITHMS FOR IRREDUNDANCY TEST In this section we describe a strategy for identifying the redundant, i.e., non irredundant, cells in a lattice. Recall that an irredundant lattice is fully testable under the SAFM. Moreover, recall that in our analysis we only consider stuck-at-faults in non-constant cells, i.e., only stuck-at-faults at the literals that control the switches. We first describe a methodology to test whether a given cell in a lattice is 0-irredundant (resp., 1 irredundant). Algorithm 1 shows the strategy based on Theorem 3: a cell c, in the lattice L, is 0-irredundant if and only if c is essential, i.e., there exists at least one miniterm v in the on-set of f L whose accepting paths always contains c.
Algorithm 1: Algorithm for the testing of the 0irredundancy of a cell c. The algorithm starts from the given cell c (containing the literal l) and considers any sub-path p T in the lattice from one top cell to c (where c is non included in p T ). If p T contains l the path is discarded since the SA0 in c will not change the output of any minterm computed by L through p T . Moreover, if p T contains a variable x and its complement x any path containing as a prefix p T outputs 0. Thus, the output is not affected by the SA0 in c and p T can be discarded. Any other sub-path p T is consider in combination with a sub-path p B from c to a bottom cell of L. Again, we can discard some of the sub-paths p B in a similar way. In order to check if c is essential, we are left to consider any minterm m of the product p associated to p T , l, p B and test if m is in the on-set of L c←0 . Note that, we can omit to test the minterms in the product associated to p T , l, p B since we have c = 0 in L c←0 . If we find a minterm of p that outputs 0 in L c←0 , the fault is testable.
Algorithm 2 shows the strategy based on Theorem 2: a cell c (containing the literal l), in the lattice L, is 1-irredundant if and only if there exists a path p that contains the cell c and is prime with respect to l, i.e., the product associated to the sequence of literals obtained removing l from the path is not an implicant of the function implemented by L. if (pB contains l) discard pB; if (pT pB contains x and x) discard pB; else forall minterm m of the product associated to pT , l, pB if m is not in the on-set of L return true ; return false; The first part of the algorithm is similar to Algorithm 1. In order to check if there exists a path p that contains the cell c and is prime with respect to l, we are left to consider any minterm m of the product p associated to p T , l, p B and test if m is in the on-set of L.
It is easy to see that a lattice L can be modeled with an undirected graph G L = (V, E) where each vertex v in V corresponds to a cell c in L and it is labeled with the literal in c. The edge (v, w) is in E iff the vertices v and w correspond to adjacent cells in L. A vertex corresponding to a cell in the top (resp., bottom) row is a top (resp., bottom) vertex . Both the algorithms consider sub-paths from top cells to c and from c to bottom cells. They can be easily implemented by DFS visits in the graph G L from c to top (resp., bottom) vertices.
The final test in both algorithms can be implemented by OBDD based methods, as classically performed in SOP forms for primality and irredundacy test. More precisely, we need to build the OBDD representing the target function f computed by L, and the OBDD containing all products associated to a satisfiable path through c. The two algorithms have then time complexity polynomial in the size of the OBDDs and the graph G L . An alternative strategy is a simulation in the given lattice L and in the transformed ones L c←0 and L c←1 . The irredundacy of the overall lattice is simply tested by applying the 0-irredundant and 1-irredundant tests on all the non-constant cells of the lattice.

VI. EXPERIMENTAL RESULTS
In this section we discuss the experiments aimed at evaluating the testability of switching lattices synthesized with the recent methods presented in [5], [13]. These experiments are based on the fault injection in lattices by substituting a literal controlling a single cell with a SA1 or a SA0. The fault injection procedure is repeated for each cell of the lattice.
The defect simulations have been run on a machine with two AMD Opteron 4274HE for a total of 16 CPUs at 2.5 GHz and 128 GByte of main memory, running Linux CentOS 7. The benchmarks functions are expressed in PLA form and are taken from a subset of LGSynth93 [19]. A total of about 580 functions were considered, and for each function each output is implemented as a separate Boolean function. The software used for simulations is written in C++. We used ESPRESSO to implement the method described in [5], and a collection of Python scripts for computing minimum-area lattices by transformation to a series of SAT problems, to simulate the results reported in [13]. Table I reports a sample of benchmark functions, referring to lattices synthesized as described in [5] and [13]. The benchmarks synthesized with [13] method were stopped after ten minutes of each SAT execution. The first column in the table reports the name and the number of the considered output of each function. The following columns report, for each synthesis method, the dimension (r × s, and area) of the lattice, and the percentages of 0-redundant and 1-redundant cells. Table II describes the overall results for the benchmarks  we considered, and it shows the average values for lattice area and percentages of 0-redundant and 1-redundant cells.
We can note that the percentage of cells that are redundant is higher in the [5] synthesis method. This is due to the more constrained structure of the lattices. Indeed, the method proposed in [5] computes a lattice that implements both the target function and its dual, and is in general less compact than the corresponding lattice given by [13].

VII. CONCLUSION
In this paper we have analyzed the testability of switching lattices under the SAFM, and characterized the properties of fully testable lattices. We have also proposed an algorithm to detect redundancies.
Future work includes the design of a method to transform non testable lattices into testable ones, by replacing some literals with a constant value, without changing the implemented function.

VIII. ACKNOWLEDGMENTS
This project has received funding from the European Unions Horizon 2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178.