A novel silicon heterojunction IBC process flow using partial etching of doped a‐Si:H to switch from hole contact to electron contact in situ with efficiencies close to 23%

We present a novel process sequence to simplify the rear‐side patterning of the silicon heterojunction interdigitated back contact (HJ IBC) cells. In this approach, interdigitated strips of a‐Si:H (i/p+) hole contact and a‐Si:H (i/n+) electron contact are achieved by partially etching a blanket a‐Si:H (i/p+) stack through an SiOx hard mask to remove only the p+ a‐Si:H layer and replace it with an n+ a‐Si:H layer, thereby switching from a hole contact to an electron contact in situ, without having to remove the entire passivation. This eliminates the ex situ wet clean after dry etching and also prevents re‐exposure of the crystalline silicon surface during rear‐side processing. Using a well‐controlled process, high‐quality passivation is maintained throughout the rear‐side process sequence leading to high open‐circuit voltages (VOC). A slightly higher contact resistance at the electron contact leads to a slightly higher fill factor (FF) loss due to series resistance for cells from the partial etch route, but the FF loss due to J02‐type recombination is lower, compared with reference cells. As a result, the best cell from the partial etch route has an efficiency of 22.9% and a VOC of 729 mV, nearly identical to the best reference cell, demonstrating that the developed partial etch process can be successfully implemented to achieve cell performance comparable with reference, but with a simpler, cheaper, and faster process sequence.


| INTRODUCTION AND MOTIVATION
The silicon heterojunction interdigitated back contact (HJ IBC) solar cell technology has enabled the achievement of solar cell power conversion efficiencies above 25% 1,2 , with the world record efficiency standing at 26.7% for single-junction crystalline silicon solar cells. 3,4 Hydrogenated amorphous silicon (a-Si:H) used as passivating contacts in this technology is key to reaching high open-circuit voltages (V OC ) up to 750 mV 5,6 by suppressing surface recombination current, while the IBC architecture ensures high short-circuit current densities (J SC ) above 42 mA/cm 23 by eliminating optical shading and parasitic absorption losses at the front side.
Our baseline HJ IBC process flow is described in Figure 1. The main challenge for this cell technology is the reduction of the process complexity on the rear-side, which requires the realisation of both the interdigitated pattern of a-Si:H strips of opposite polarities as well as interdigitated metal fingers contacting these strips. Lab-scale approaches typically involve photolithography 2,7 for patterning, 2 to 3 alignment steps, several cumbersome wet processes, and a large number of steps, which reduce the throughput and processing reliability and increases the cost of solar cell fabrication. Therefore, several groups investigating this cell architecture focus on not only on performance improvement but also simplification of the rear-side process sequence. For industrial viability, the target is to attain a lithographyfree process sequence, consisting of a minimum number of steps, preferably without using many dangerous chemicals leading to lower processing costs, greater process reliability, and higher throughput.
While well-known techniques such as screen-printing and inkjet printing can be used for metal finger patterning, [8][9][10] it is the patterning of the a-Si:H strips that is the most challenging. The simplest approach that has been investigated is the use of mechanical shadow masks to deposit, in an additive fashion, successively the two juxtaposed finger patterns of opposite polarity in just 2 steps. 8,[11][12][13] As a further simplification, a novel "tunnel-IBC" structure, requiring just a single alignment step, has been implemented with great success. 9 In addition, the entire patterning sequence is completed in situ and without wet chemical treatments during the patterning. While this is very advantageous, the industrial compatibility of using reusable shadow masks is debatable.
Moreover, depositions through masks lead to tapered profiles of deposited films and require proximal contact of wafers with the masks. 14 Another popular "litho-free" alternative to patterning, which is contact-less and also drastically reduces the number wet chemical steps, is laser ablation-assisted patterning. [15][16][17][18][19][20] In this approach, the pattern is often directly structured onto a sacrificial mask layer on top of the a-Si:H stack to be patterned. While there is a risk of laser-induced thermal damage to the crystalline silicon and the heterocontact in the laser-ablated areas, 19,20 significant strides have been made recently in tackling this issue. 17 In this approach, etching of the underlying a-Si:H stack is needed, and hence, it is a subtractive route, just like in photolithography. Often, wet etching is used, which is not well-controllable and can lead to processing issues. 18,21,22 Dry etching can considerably improve process reliability. 21 One of the strategies to simplify our baseline process sequence (depicted in Figure 1, left) into a simpler one that is litho-free, almost alldry, and inexpensive is shown in Figure 1 (middle). We have shown in our recent work the successful replacement of lithography by laser ablation 3 , and wet etching by dry etching . 21 In this paper, the development of the partial dry etch route, which eliminates the ex situ wet clean step, will be discussed. Such a sequence can be completed fully in situ, requires no use or disposal of dangerous wet chemicals such as hydrofluoric acid (HF), has higher throughput and is also more reliable for the processing of glass-bonded thin silicon (depicted in Figure 1, bottom right).
A part of the HJ IBC rear-side process sequence is depicted schematically in Figure 2. In the baseline process flow, after hard mask patterning, the areas with exposed a-Si:H (i/p + ) are completely etched to reveal the crystalline Si surface using NF 3 /Ar plasma-based dry etching in the same PECVD tool used to deposit a-Si:H . 21 After dry etching, the surfaces are cleaned ex situ using an HF dip to remove residual contaminants on the surface before being inserted back into the PECVD tool for the deposition of a-Si:H (i/n + ), thereby producing interdigitated strips of a-Si:H (i/p + ) and a-Si:H (i/n + ), following a subsequent lift-off step.

FIGURE 1
The baseline heterojunction interdigitated back contact (HJ IBC) process flow (left). Process simplifications leading to an all-dry, lithofree, cost-effective a-Si:H patterning sequence are also indicated (middle). Cross-sectional schematics of a freestanding and a glass-bonded HJ IBC cell are given on the right [Colour figure can be viewed at wileyonlinelibrary.com] When processing glass-bonded HJ IBC devices, achieving and maintaining excellent rear surface passivation in the presence of bonding agents (silicones or ethylene-vinyl acetate [EVA]) is a challenging integration problem. 23,24 This is because bonding agents contain volatiles that can outgas during the passivation process resulting in poor passivation. To address this, an extended outgassing step and in the case of silicones, an Ar plasma treatment step are applied to ensure reproducible high-quality passivation, 25 as shown in Figure 3B. These processes, however, are not permanent fixes for the outgassing issue.
Thus, any re-exposure of the crystalline silicon surface during subsequent processes (eg, after dry etch) can lead to problems with the repassivation of the re-exposed areas, because of the same organic contamination issue, as depicted in Figure 3A. Figure 3C shows the PL image after repassivation of dry-etched areas, having an outgassing pattern from the edges, which is indicative of organic contamination from the exposed silicone at the wafer periphery.
The partial etching route (Figure 2, bottom) can solve these issues, whereby dry etching is carefully controlled to remove only the doped layer (p + a-Si:H), leaving behind the intrinsic a-Si:H layer from the first passivation and not re-exposing the crystalline silicon surface. In the FIGURE 3 A, schematics depicting outgassing of organic contamination from the bonding agent onto the re-exposed c-Si surfaces and the resulting poor repassivation. B, and C, photoluminescence (PL) images showing the passivation quality during rear-side processing of heterojunction interdigitated back contact (HJ IBC) cells on glass-bonded silicon [Colour figure can be viewed at wileyonlinelibrary.com] next step, n + a-Si:H is deposited in situ without vacuum break, in a single pump-down process. Skipping the ex situ wet clean can also reduce the process time and enable a fully in situ all-dry process sequence from dry etching till repassivation. This is particularly favourable for module-level cell processing 26,27 since wet processing of large-area glass is prohibitively cumbersome.
In this paper, for the development of the partial dry etch route, as depicted in Figure 1, freestanding wafers are used. However, the process is fully applicable to and compatible with glass-bonded wafers. Moreover, the newly developed process sequence is implemented using our photolithography baseline and will be later integrated with laser ablation.

| Samples for surface passivation quality evaluation
N-type, 200 μm thick, 156 × 156 mm 2 semi-square, 3 to 5 Ω.cm, (100) Cz wafers were first etched in a hot potassium hydroxide (KOH) bath to remove the saw damage from the wafering process. Subsequently, the wafers were cleaned in a bath containing ozone and deionised water (DIW:O 3 ) for 5 minutes, followed by an HF dip, to produce hydrophobic surfaces. The non-investigated side of the wafers was passivated with a stack of a-Si:H (i/n + ) using PECVD at 175°C that results in excellent surface passivation. The investigated surface of these wafers was passivated using a stack of either a-Si:H (i/n + ) or a-Si (i/p + ). Partial etching was investigated on both polarities of doping. Passivation quality was evaluated using photoluminescence (PL) and injection level-dependent minority carrier lifetime measurements by means of quasi-steady state photoconductance (QSSPC).

| Samples for contact resistivity measurements
Selected samples used for passivation tests above were further used to evaluate contact resistivity. The rear-side a-Si:H (i/n + ) passivation was removed using standard NF 3 Figure 1. The partial etch sequence developed in this work is integrated into this baseline process flow. For comparison, reference wafers following the conventional process sequence were also co-processed in the same run. The details of the different solar cell fabrication processes used in this work have already been described in detail in our previous publications. 21,30 Here, only the salient features and key differences between the two splits are highlighted.
Although it is possible to pattern either the a-Si:H (i/p + ) hole contact or the a-Si:H (i/n + ) electron contact first, we chose to deposit and pattern the hole contact first. A hard mask consisting mainly of PECVD silicon oxide (SiO x ) is deposited on the a-Si:H (i/p + ) stack. Photolithography, dry etching, and lift-off 21,30 are used to produce interdigitated strips of a-Si:H of opposite polarities on the rear side. For the conventional route, the a-Si:H (i/p + ) hole contact areas exposed by the hard mask is etched off completely using NF 3  Finally, an n + a-Si:H layer is deposited, again in situ, to form the a-Si:H (i/n + ) electron contact. All other process steps are identical for the two routes, as depicted in Figure 1, and explained in detail in another study. 21,30 Two wafers were processed for each split. A total of 16 cells

| DEVELOPMENT OF PARTIAL DRY ETCHING OF A-SI:H
For a reliable and successful partial etch process, the following criteria must be achieved: 1. The etched thickness must be well-controllable (ie, low etch rate of < 0.5 nm/s and good spatial uniformity).
2. High surface passivation quality must be attained (ie, no plasma damage or contamination).
3. Contact resistivity values must be comparable with that of reference samples (ie, the quality of the contact layers should not be adversely affected by the partial etch process)

| Selection of partial etch conditions
The standard dry etch process for removing a-Si:H in the baseline flow ( Figure 1) is based on NF 3 /Ar plasma with a flow ratio of NF 3 : Ar = 200:100 sccm. 23 This results in an etch rate of approximately 1.5 nm/s, which is too high to achieve a well-controllable partial etch process. On the other hand, with H 2 plasma etching, a wellcontrollable etch rate of approximately 1 nm/min is attainable. However, the low etch rate and the consequently prolonged etch durations in the order of several minutes would result in severe plasma damage to the crystalline silicon bulk even at low power, as revealed by minority carrier lifetime measurements and deep-level transient spectroscopy (DLTS). 21,31,32 Thus, NF 3 /Ar plasma-based dry etching is the preferred choice for the partial etch development.
During NF 3 /Ar plasma dry etch, F * radicals are formed in the plasma, which react with Si atoms on the wafer surface. Ar + ions assist in providing energy for these reactions via physical bombardment. In this way, Si atoms are removed as SiF 4 gas during the etch process. 33 Therefore, the etch rate can be reduced by increasing the NF 3 gas dilution in the chamber, by reducing the NF 3

| Evaluation of surface passivation in the partial etch route
As mentioned before, an important criterium for the rear-side patterning process is that the rear-side passivation quality should not be adversely affected such that high-quality passivation is maintained throughout the patterning sequence. There are several risks associ-  Overall, the process window of the developed partial etch process for a 21 nm-thick p + a-Si:H layer on blanket samples is between 65 seconds (just enough to remove the entire p + a-Si layer) and 78 seconds (leaving behind just enough intrinsic a-Si:H layer to maintain good passivation), which corresponds to about 13 seconds (roughlỹ 20% of the total process time). We believe that this process window is large enough for a reliable partial etch process. For device processing, we target approximately the middle of the process window. As

| Unexpected blistering of doped a-Si:H deposited on partially-etched a-Si:H
A problem that arose during the partial etch development is the unex-  A revealed that the thickness at location "A" corresponded to the remnant a-Si:H after partial etch, while that at location "B" corresponded to the total thickness of the remnant a-Si:H plus the p + a-Si:H layer deposited on top. This spontaneous blistering happens also when the partial etch process is carried out on a stack of a-Si:H (i/p + ) with a subsequent deposition of an n + a-Si:H layer. As indicated in Figure 7B, the fractions of blistering events after a partial etch process is approximately 80%, which is very high.
Although it is not fully clear why this blistering occurs, it has been shown in our previous work that NF 3 /Ar plasma etching process leads to a residual layer on the surface at the end of the process. 33 This layer is dissolvable in an HF solution. It is hypothesized that this residual layer could be the root cause of the observed spontaneous blistering. To verify this, partially-etched samples were dipped in a HF bath for 1 minute to remove the dry etch residual layer before deposition of the second doped layer. This ex situ HF clean solves the issue, whereby no incidents of blistering were observed on such samples, as shown in Figure 7B. However, since one of the goals of the partial dry etch process is to perform the entire sequence in situ, without taking the wafers out of the PECVD tool, a dry clean method was introduced. A short H 2 plasma treatment, which does not contain contaminating species, was used to etch off the residual layer at a moderate power density of approximately 90 mW/cm 2 for 30 seconds.
As shown in Figure 7B, this in situ clean also solves the blistering issue, thus enabling a fully in situ partial etch process. To verify that the H 2 plasma treatment inserted after the partial etch does not affect the lifetime, a passivated wafer was subjected to the full in situ partial etch process. As shown in Figure 7C, the short H 2 plasma treatment does not degrade the lifetime of the wafer.

| Evaluation of contact resistivity
Since the a-Si:H (i/doped) stack is actually part of the contact, any modification of the a-Si:H structure by the partial etch process may affect the charge carrier transport across the a-Si:H layers, even though the surface passivation might be excellent. Contact resistivity measurements, performed as described in Section 2.3 and by Cho et al, 29 on the a-Si:H (i/n + ) electron contact formed using the partial etch sequence as well as the conventional route are compared in where ΔFF Rs is the fill factor loss due to series resistance, J mpp and imately 0.3% compared with our reference cells. We believe that improvements to the in situ hydrogen plasma treatment after the partial dry etch would help to reduce the contact resistivity, and will be the focus of future improvements to this process.

| CELL INTEGRATION OF THE PARTIAL ETCH PROCESS
The developed in situ partial dry etch route was implemented in our HJ IBC process flow on 200 μm-thick, n-type (100) FZ Si wafers, as described in Figure 1. For comparison, wafers following the conventional process sequence, with a full dry etch and an ex situ wet clean, were coprocessed as the reference split. The average and best cell parameters determined from light IV cell measurements are summarised in Table 1.
The IV characteristics of the best cell from the reference split and that from the partial etch split are plotted together in Figure 9.
First and foremost, functional cells were produced for the first time using a completely in situ partial etching route. The PL image of a wafer, consisting of a total 16 cells, after the rear-side patterning of a-Si:H strips is shown in the inset of Figure 9. Uniform passivation has been achieved across the entire wafer. The lack of significant contrast in the PL intensity between the electron and hole contact areas within a single cell implies that similar quality passivation has been achieved in both areas, where the n-doped area had undergone the partial etch process. As shown in Table 1, the reference process resulted in excellent V oc values close to 730 mV, indicating high-quality surface passivation. Cells from the in situ partial etch split also showed high-quality passivation with V oc values comparable with reference. This corroborates well with the lifetime results described in Section 3.2 and the PL image in the inset of Figure 9.
In general, all cells suffer from moderate FF values around 75%. A FF loss analysis, performed according to, 41 shows that the FF of our reference cells is typically limited by series resistance (approximately 5% absolute) and J 02 -type recombination (approximately 4% absolute) losses. In addition to the FF values, the series resistance at device level obtained using the Bowden method 42 and the fill factor loss due to series resistance calculated using Equation 1 are also given in   Overall, the best efficiency achieved with the reference split is 22.9%. With the newly-developed in situ partial etch route, the same best efficiency of 22.9% is attained for the best cell, thus proving that a similar performance to reference can be achieved with a simpler process sequence. In future, cell performance could be further enhanced by optimising the partial etch process with improved in situ hydrogen plasma treatment and better spatial uniformity.

| CONCLUSIONS AND OUTLOOK
We have developed a novel in situ partial dry etch process sequence for HJ IBC solar cells, whereby the doped a-Si:H on the rear-side is switched by etching off the exposed p + a-Si:H (or n + a- indicating that the charge carrier transport across the a-Si:H contacts is not drastically affected by the newly-developed process.
Finally, the partial etch route was implemented in the HJ IBC process flow, resulting in excellent V oc values close to 730 mV, which can be attributed to the high-quality passivation attainable with the partial etch process. While the FF loss due to series resistance appears to be higher for the partial etch split, FF loss due to J 02 -type recombination is lower. This provides room for further improvement of the developed process.
Overall, a best efficiency of 22.9%, identical to the reference split was achieved, proving that the partial etching route can attain similar cell performance as the reference route, while simplifying the rear-side process sequence. The process simplification implemented in this work eliminates the need to remove the wafers from the PECVD tool after dry etch and the need to use a cumbersome wet cleaning step in between dry etching and repassivation. Moreover, use of dangerous chemicals such as HF and the associated chemical waste disposal can be minimised. Such a process sequence is also beneficial for processing of glass-bonded samples (in module-level cell processing concepts), since crystalline silicon surface re-exposure is avoided, thus maintaining high-quality surface passivation throughout the rear-side process sequence. This approach not only increases the processing simplicity but also improves the throughput. The next step of this work will focus on further optimisation of the partial etch process to improve the contact resistivity and subsequently on the implementation of the partial etch sequence together with laser ablation patterning. The efficacy of this approach on fully and partially textured rear-side will also be evaluated.

FIGURE 9
The current-voltage characteristics under AM1.5G illumination of the best cell from the partial etch route and that from the reference conventional process sequence. Inset shows the uncalibrated PL image of a wafer after the rear-side a-Si:H patterning, from the partial etch route [Colour figure can be viewed at wileyonlinelibrary. com]