Principle and Topology Derivation of Single-Inductor Multi-Input Multi-Output DC–DC Converters

Single-inductor multi-input multi-output (SI-MIMO) dc–dc converters are attractive in the engineering applications due to the advantage of high power density and low cost. In order to explore as many as possible SI-MIMO topologies, this article proposes a simple and effective topology derivation principle that only requires three steps. First, three basic cells consisting of a single inductor and multiple sets of unidirectional switches as well as inputs/outputs are proposed. Second, integrate the mentioned three basic cells with the inductor branch of the typical single-input single-output converters. Finally, implement the topology simplification by removing unnecessary switches/diodes. Based on the proposed principle, a large number of SI-MIMO topologies are derived from buck, boost, buck–boost, and noninverting buck–boost converters in this article. With more topology choices having different performance characteristics, it is very beneficial for engineers to gain an optimized design that a preferred one can be selected out after comprehensive comparison. As an example, topology comparison and selection among a family of single-inductor single-input dual-output converters is also conducted in this article. Besides, performance analysis, design considerations, and simulation/experiment results of the selected optimum topology are demonstrated in detail to verify its advantages.


I. INTRODUCTION
I N MANY industrial applications, such as photovoltaics [1], [2], electric vehicles [3], data processing centers [4], personal computers [5], and so on [6]- [8], multiple ports with various voltage levels are demanded. In order to achieve the voltage regulation as well as the power control among different ports, multiple independent single-input single-output (SISO) converters can be simply employed. However, owing to the large number of components, high overall cost and large system volume will be incurred. To address this problem, two types of integrated multiport dc-dc converters have been proposed, in which the number of semiconductor devices and inductors is effectively reduced, and so that both the cost and power density are improved.
Based on the typical buck [9], [10], boost [11], and buckboost [12] converters, integrated N-port converters with semiconductor devices multiplexed were proposed, which only need N switches/diodes. In comparison with the conventional solution with N independent SISO converters, including 2N−2 switches/diodes, the number of semiconductor devices is N−2 reduced, and hence lower cost can be achieved. Aiming to explore more favorable topologies, a systematic synthesis method was further proposed in [13]. However, because the magnetic components accounting for a very large proportion in the overall volume and weight are not optimized, the improvement of power density is limited in the integrated multiport converters with semiconductor devices multiplexed.
Fortunately, the inductor can also be multiplexed, and only one inductor is employed in the single-inductor multi-input multi-output (SI-MIMO) converter. The inductor functions as a common power flowing path for different ports. Consequently, high power density is achieved in the SI-MIMO converters, which attract increasing attention in the recent years. In general, researches of SI-MIMO converters mainly focus on two aspects, new control and new topologies, to improve converter performance. In terms of the control strategy, there are three common modulation strategies, discontinuous conduction mode (DCM), continuous conduction mode (CCM), and pseudo-CCM/DCM. In [14], the converter is designed to work in DCM with multiple energizing cycles per switching period. It functions similarly as multiple independent SISO converters, and thus good dynamic response is achieved. However, under heavy load conditions, the peak inductor current will become large, which deteriorates both the current stresses and conduction losses. In order to alleviate this problem, the SI-MIMO converters can work in CCM with one energizing cycle per switching period. Nevertheless, because the power transfer among different ports are dependent on a common inductor, severe cross-regulation problem will be caused. Based on this, multiple new control schemes had been figured out in the past researches, aiming to achieve reduced cross regulation. Besides the CCM and DCM, the SI-MIMO converters can also work in pseudo-CCM/DCM with an extra switch connected between the inductors [15], [16]. It makes a compromise between the current stresses and the cross-regulation problem. In a word, control strategies of SI-MIMO converters have been widely studied in the past.
On the other hand, in terms of the topology configurations, only several SI-MIMO dc-dc converters have been proposed in the existing researches. Six types of single-inductor single-input dual-output (SI-SIDO) topologies based on buck [17]- [19], boost [17], [20], buck-boost [17], or noninverting buck-boost [17], [21], [22] converters were presented, and four types of single-inductor multiple-input single-output topologies based on buck [23], boost [24], buck-boost [23], and noninverting buck-boost [25] converters were proposed. In addition, their counterpart MIMO converters were developed in [26]- [32] by simply connecting multiple additional input/output branches in parallel. Although the existing topologies can provide favorable performances for the specified applications, they cannot always be the best choices for various applications with different system requirements. For example, for the applications having several inputs/outputs with different voltage/power levels, the direct parallel connection of additional input/output branches is usually not a good solution. Actually, in order to effectively select a preferred converter for an engineering application, as many viable topologies as possible should be provided and compared. However, until now, the principle to derive SI-MIMO topologies is kept unclear, and only a limited number of topologies is available.
From the abovementioned information, SI-MIMO converters have the advantages of low cost and high power density, which are attractive in the engineering applications. Their control strategies have been widely discussed in the relevant researches to improve the dynamic characteristics. But for the topology configurations, only several ones are available, and more viable topologies are desired so that a preferred one can be selected out after comprehensive comparison. With this demand, a novel principle of deriving a large number of SI-MIMO topologies from typical buck, boost, buck-boost, and noninverting buckboost SISO converters is proposed in this article. Only three steps are needed, and thus it is simple to be implemented. To gain a better understanding, a family of SI-SIDO, single-inductor dual-input single-output (SI-DISO), and single-inductor dualinput dual-output (SI-DIDO) topologies are derived and demonstrated, including the ones presented in [17]- [22]. Besides, the obtained SI-SIDO boost converters are taken as an example to be compared, and an optimum one is finally chosen for a specific application, whose performance analysis, design considerations, and simulation/experiment verification are also illustrated in detail.

II. PRINCIPLE AND TOPOLOGY DERIVATION
In this section, the principle and topology derivation of SI-MIMO converters from the typical buck, boost, buck-boost, and noninverting buck-boost SISO converters in Fig. 1 will be depicted in detail, which only needs three steps and thus can be implemented easily. Besides, some of the derived topologies can be further simplified under appropriate working conditions to obtain reduced number of semiconductor devices.

A. Principle
First, three basic MIMO cells (MIMO_1, MIMO_2, and MIMO_3) with p outputs and q inputs are proposed in Fig. 2, according to the fundamental operation principle and topology structure of the existing SI-MIMO converters. By connecting multiple inputs/outputs and unidirectional switches with the outflow, inflow, or both ports of inductor, as shown in Fig. 2(a)-(c), the current i L will be multiplexed and will flow into different inputs/outputs during the time interval when their corresponding switches conduct.
Second, integrate the MIMO cells shown in Fig. 2 with the inductor branch of buck, boost, buck-boost, and noninverting buck-boost converters. In order to achieve a unified topology derivation process, the inductor branch of four typical SISO converters are expressed in a general form, as shown in Fig. 3(a). According to Fig. 1, the values of m and n are either 1 or 2. Then, the integration of one MIMO cell and the inductor branch is depicted in Fig. 3(b)-(d). For the MIMO_1 cell, it is added at the outflow port of inductor, and an extra unidirectional switch is added in each original branch B o1 -B on . These additional  switches along with the switches in MIMO_1 cell are used to ensure that inductor current i L can only flow into one path at any time. The integration is similar for the MIMO_2 cell, as shown in Fig. 3(c), whereas it is a little different for the MIMO_3 cell. From Fig. 3(d), only an extra unidirectional switch is needed for the integration of MIMO_3 cell, because it is parallel connected with the inductor. Moreover, two or three different MIMO cells can also be simultaneously integrated with the SISO converters in a similar manner, as shown in Fig. 4. It is noted that the extra unidirectional switch connecting with MIMO_3 in Fig. 3(d) can be removed when it is combined with MIMO_1, MIMO_2, or both, as illustrated in Fig. 4 For the SI-MIMO topologies presented in Figs. 3(b) and (c) and 4(a)-(d), which employ MIMO_1 cell or MIMO_2 cell, one port of each output V o1 -V op or input V i1 -V iq is suspended. Theoretically, the suspended ports can be connected to any nodes of typical SISO converters other than the two nodes of inductor, and hence more than one SI-MIMO topology can be correspondingly developed. In the following section, it is shown that with the integration of MIMO_1 cell or MIMO_2 cell, two SI-SIDO/SI-DISO topologies can be derived from the buck, boost, as well as buck-boost converters and three topologies for noninverting buck-boost converters.
Finally, simplify the above derived SI-MIMO topologies by removing unnecessary switches. It is obvious that there are unnecessary switches since many extra unidirectional switches are  added. Some of them are reduplicated and some are useless. As shown in Fig. 5, two MOSFETs/diodes connected in series are reduplicated, and it can be simplified by deleting the reduplicated one. Furthermore, denote the voltage across the unidirectional switch consisting of a MOSFET and a diode as v s . If it is larger than or equal to zero all the time, the diode will always be forward biased, and thus it can be removed. On the other hand, if v s is always less than or equal to zero, the parallel diode of MOSFET conducts all the time, and it can also be removed.

B. Topology Derivation
With the abovementioned principle, various SI-MIMO converters can be easily derived. Taking the combination of boost converter and MIMO_3 cell with one output branch (p = 1, q = 0) as an example, its detailed topology derivation process is demonstrated in Fig. 6. After integrating MIMO_3 cell with the boost converter in Fig. 6(a), the extra unidirectional switches are moved to connect in series with switch S 1 and diode D s2 , as shown Fig. 6(b). According to the simplification shown in Fig. 5, the reduplicated MOSFET and diode are deleted in Fig. 6(c). Then, by turning ON the switch S 1 , S 2 and S 3 one-by-one, the inductor current i L will flow into a different path in a switching period. When S 1 is OFF, the voltage across D s1 and S 1 is equal to V o1 and V i1 + V o2 in the interval with S 2 and S 3 ON, respectively. Therefore, it is always larger than zero, and the diode D s1 can be further removed. Finally, a viable SI-SIDO topology is derived in Fig. 6(d). To the best knowledge of the authors, this topology has not been reported in previous researches.
In addition, Tables I and II also summarize a family of SI-SIDO and SI-DISO converters derived from typical buck, boost,  I  FAMILY OF SI-SIDO CONVERTERS DERIVED FROM BUCK, BOOST, BUCK-BOOST, AND NONINVERTING BUCK-BOOST CONVERTERS buck-boost, and noninverting buck-boost converters using the proposed topology derivation method. 5, 5, 3, and 7 viable SI-SIDO/SI-DISO topologies are respectively obtained, among which there is always one including MIMO_3 cell.
According to Fig. 1, except for the two nodes of inductor, there are two other nodes in the buck, boost, and buck-boost converter, and hence two corresponding topologies can be respectively obtained for them by integrating one MIMO_1 or MIMO_2 cell. It is noted that the SI-SIDO/SI-DISO buck-boost topologies consisting of MIMO_1 or MIMO_2 cells are the same, because its outflow and inflow ports of the inductor are equivalent. For the noninverting buck-boost converters, there are three other nodes, and likewise, three topologies are derived with MIMO_1 or MIMO_2 cell. In these SI-SIDO/SI-DISO topologies, several ones have been presented in [17]- [22], and the rest are first found with the proposed principle in this article. Because their performance characteristics are different, engineers can select a preferred one for a specified application after comprehensive comparison, which is very beneficial for the practical design. And in order to help engineers to better select the required topology, the basic voltage and current requirements of topologies are summarized in Tables I and II, respectively, according to the voltage-second balance and ampere-second balance. Taking the topology presented in Table I(ii)-(a) as an example, the inductor voltage will be equal to Hence, V i1 must be smaller than V o1 + V o2 , otherwise the average voltage of inductor in a switching period would not be zero. In addition, according to the ampere-second balance of capacitor, the average current I o1 of first output is equal to the sum of the average current I o2 of second output and the current of unidirectional switch. Therefore, I o1 > I o2 is obtained, and it is compulsory to use first output V o1 to guarantee the normal operation of second output V o2 . It is noteworthy that the requirements can be further refined if more specified parameters are provided.
Moreover, with the increasing number of ports, more viable SI-MIMO topologies can be developed. Taking the SI-DIDO topologies based on a boost converter as an example, it has 25 viable topologies in total, which can be classified into 6 types in terms of the different MIMO cells. An example topology of each type is respectively demonstrated in Fig. 7. In Fig. 7(a)-(c), two same MIMO cells are added in the boost converter simultaneously, whereas two of three cells are combined in Fig. 7(d)-(f). In comparison with the SI-MIMO converters that have multiple additional inputs/outputs only connecting in parallel [26]- [31], the characteristics of additional ports in the newly obtained

C. Further Discussion
Actually, some of the above derived SI-MIMO topologies can be further simplified if they work under appropriate voltage conditions. According to Fig. 5, the MOSFET or diode will become useless in their series-connected structure if its voltage is always positive or negative and, thus, can be deleted. Taking the SI-SIDO converters based on boost converter in Table I(ii) as an example, topologies presented in (b), (c) and (e) can be, respectively, simplified into the ones presented in Figs. 8-10, when the corresponding relationships among V i1 , V o1 , and V o2 are satisfied. After simplification, the number of required semiconductor device is reduced and so is the conduction losses.

A. Topology Comparison
After deriving various SI-MIMO topologies, their performance characteristics will be compared and then an optimum one could be selected out for a specified application. As an example, the obtained SI-SIDO topologies based on a boost converter presented in Table I(ii) and Figs. 8-10 will be detailed compared in this section. Afterward, topology selection is conducted for a specific application with input voltages V i1 = 18-30 V, output voltages V o1 = 60 V, V o2 = 24 V. Because V o2 is always smaller than V o1 and V o1 − V i1 , the SI-SIDO boost converters presented in Table I( Table III. For the topologies presented in Table I(ii)-(a) and Fig. 8(a), their average inductor currents are smaller, which is equal to the input currents I i1 , and the number of active semiconductor devices in conduction is also smaller. However, their working conditions are limited. The output current I o2 must be less than I o1 in Table I(ii)-(a), and the relationship between I o1 and I o2 is restricted under the condition with V o2 < V i1 in Fig. 8(a), e.g., I o1 cannot be no-load with V o2 < V i1 , otherwise the inductor will be always charged. In a word, although the topologies presented in Table I(ii)-(a) and Fig. 8(a) are favorable in terms of the average inductor current and semiconductor devices, they   Table I Table I Table I III  COMPARISON AMONG AVAILABLE SI-SIDO TOPOLOGIES PRESENTED IN  TABLE I( are not suitable for the specific application due to the restricted working conditions. The undesired restriction is avoided in the topologies presented in Fig. 9(a), Table I(ii)-(d), and Fig. 10(a). And I L is equal to I i1 + I o2 in all these three converters. Their differences mainly lie in the number of active semiconductor devices in different working stages. From Table III, all working stages have two active semiconductor devices in the topologies presented in Fig. 9(a) and Table I(ii)-(d), whereas only one stage has two and the rest two stages have one in the topology presented in Fig. 10(a). Therefore, thanks to the smaller number of active semiconductor devices in conduction and consequently lower conduction losses, the topology presented in Fig. 10(a) is chosen for the specific application.

B. Operation Analysis
The proposed SI-SIDO topology shown in Fig. 10(a) is redepicted in Fig. 11(a). It can operate in DCM, as shown in Fig. 12(a), or CCM, as illustrated in Fig. 12(b). v gs1 and v gs3 are the drive signals of S 1 and S 3 , respectively. i L , i s1 , i s3 , and i Ds2 are the inductor current, drain-to-source currents of S 1 , S 3, and current of D s2 , respectively. The corresponding equivalent circuits in different stages are shown in Fig. 11(b)-(e). It is noted that all components are assumed to be ideal to simplify the analysis. 1) DCM Operation: According to Fig. 12(a), a switching period T s is divided into two equal parts [t 0 , t 3 ] and [t 3 , t 6 ] in DCM. During the interval [t 0 , t 3 ], switch S 3 is turned OFF, and the power is transferred from input V i1 to output V o1 . Switch S 3 conducts during the interval [t 3 , t 6 ], and then the power is transferred from input V i1 to output V o2 . The output voltages V o1 and V o2 are, respectively, controlled by the duty cycle D 1 and D 2 of S 1 in each half switching period.
Stage 1 (t 0 -t 1 ): Switches S 1 conduct whereas S 3 is turned OFF in this stage, as illustrated in Fig. 11(b). Inductor L is charged by V i1 , and thus the inductor current i L increases. The drainto-source current i s1 is equal to i L . Two diodes D s2 and D s3 are both reverse biased, which are, respectively, clamped by V o1 and V i1 + V o2 .
Stage 2 (t 1 -t 2 ): At t 1 , switch S 1 is turned OFF, and then diode D s2 turns to be forward biased, as shown in Fig. 11(c). In this stage, inductor L is discharged by V i1 − V o1 , and thus the inductor current i L decreases. The drain-to-source current i Ds2 is equal to i L . Switches S 1 and S 3 are, respectively, clamped by Stage 3 (t 2 -t 3 ): At t 2 , the inductor current i L decays to zero. Then, all semiconductor devices are inactive in this stage, as illustrated in Fig. 11(d).
Stage 4 (t 3 -t 4 ): At t 3 , switches S 1 and S 3 are turned ON. The operation in this stage is the same as that of stage 1.
Stage 5 (t 4 -t 5 ): At t 4 , switch S 1 is turned OFF. Because S 3 is ON and V o2 + V i1 is smaller than V o1 , the diode D s3 will turn to be forward biased, and the inductor current i L commutes to output V o2 , as shown in Fig. 11(e). In this stage, inductor L is discharged by −V o2 , and thus the inductor current i L decreases. The diode D s2 and switch S 1 are, respectively, clamped by Stage 6 (t 5 -t 6 ): At t 5 , the inductor current i L decays to zero, which is the same as that of stage 3.
From above, the proposed SI-SIDO converter shown in Fig. 11(a) operates as a typical boost and buck-boost converter in turn during different half switching periods T s /2. Then, the voltage relationships among V o1 , V o2 , and V i1 can be correspondingly obtained in (1). From (1), by adjusting the duty cycles D 1 and D 2 , the output voltages V o1 and V o2 can be independently controlled. In addition, the power P o1 and P o2 of two outputs V o1 and V o2 are calculated in (2), which can also be, respectively, controlled by the duty cycles D 1 and where R 1 and R 2 are the output resistances of V o1 and V o2 , respectively.
2) CCM Operation: According to Fig. 12(b), a switching period T s includes three stages [t 0 , t 3 ] in CCM. The stages [t 0 , t 1 ], [t 1 , t 2 ], and [t 2 , t 3 ] of CCM are, respectively, similar to the stages [t 0 , t 1 ], [t 1 , t 2 ], and [t 4 , t 5 ] of DCM, except that the inductor current i L is continuous instead of discontinuous. The inductor current flows to the first output V o1 during the stage [t 1 , t 2 ] and flows to the second output V o2 during the stage [t 2 , t 3 ]. Then, with the neglect of inductor current ripple, equation can be obtained according to the flux balance of inductor. With the abovementioned two equations, the voltage relationship between V o1 , V o2 , and V i1 is calculated in (3). From (3), both V o1 and V o2 are determined by D 1 , D 3 , R 1 , and R 2 . Therefore, severe cross-regulation problem will be incurred under load variation. In order to improve the dynamic response, the existing proposed solutions, such as control loop decouple [33], [34], multivariable control [35], predictive control [36]- [38], and deadbeat control [39], can be employed, but with increased complexity ⎧ ⎨

IV. DESIGN AND EXPERIMENT VERIFICATION
In order to verify the theoretical analysis, a prototype circuit of the proposed SI-SIDO converter, shown in Fig. 11(a), with system parameters, presented in Table IV, is built. In this section, its design considerations in both DCM and CCM are explained first. Then, the simulation and experiment results under input voltages V i1 = 18 and 30 V are demonstrated.

A. Design Considerations
In DCM, the peak inductor current i L (t 1 ) and i L (t 4 ) are obtained in (4) from the performance analysis in previous section. Then, according to the average output current I o1 = i L (t 1 ) × (t 2 − t 1 )/2 and I o2 = i L (t 2 ) × (t 5 − t 4 )/2, the values of t 2 -t 0 and t 5 -t 3 are calculated in (5), and they should be less than T s /2. Based on this requirement, the available inductance L is calculated in (6) and is depicted in Fig. 13(a) with the aforementioned system parameters. The available inductance varies with different input voltages V i1 , for example, L ≤ 74 µH for V i1 = 30 V, whereas L ≤ 37 µH for V i1 = 18 V. Because the DCM operation is demanded to be guaranteed under whole input voltage range, the smallest range of inductance L should be selected, i.e., L ≤ 37 µH. Besides, with the consideration of margin and nonideal parameters in the practical circuit, the inductance L is finally designed as 30 µH. Then, the duty cycles D 1 and D 2 are derived in (7) from (1) and are also demonstrated in Fig. 13(b). They decrease with the increment of input voltage V i1 . Afterward, substituting (7) into (4), the peak inductor currents i L (t 1 ) and i L (t 4 ) as a function of V i1 are illustrated in Fig. 13(c), which, respectively, obtain maximum value 7.48 A and 5.66 A at V i1 = 18 V. Moreover, according to Fig. 12, the root-mean-square (rms) value of inductor current I L_rms and drain-to-source current I s1_rms , I s3_rms are obtained in (8). Their maximum values 3.57, 2.89, and 1.37 A are also obtained at V i1 = 18 V, as shown in Fig. 13(c) and (d). And from Fig. 11(a), the average current I DS2 -I DS3 of D s2 -D s3 are equal to the average currents I o1 and I o2 , respectively. On the other hand, the maximum drain-to-source voltages of S 1 and D s2 are V o1 , and the voltage stresses of S 3 and D s3 are V o1 − V i1 − V o2 and V i1 + V o2 , respectively. Based on abovementioned analysis, a ferrite core EI-28 with 12 turns is employed to implement the inductor L, MOSFET IPP530N15N3 is chosen as switches S 1 and S 3 , and MBR20200CT is employed as diode D s2 and D s3 in the prototype circuit .
In CCM, the required inductance is different from that in DCM, whose value is designed to ensure that the ripple current Δi L of inductor in (9) is less than 20% of its average value I L . Similarly, according to the system parameters presented in Table IV, the inductance is designed as 1.42 mH. In addition, the voltage stresses of semiconductor devices are the same as that in DCM, whereas their current stresses are decreased due to the smaller ripple current. Hence, the MOSFET IPP530N15N3 and diode MBR20200CT are still used

B. Simulation and Experiment Results
Experiment waveforms of the proposed converter in Fig. 11(a) working in DCM are illustrated in Figs. 14-16, which are in well coincidence with the aforementioned theoretical analysis. From Fig. 14, by adjusting the duty cycles D 1 and D 2 of drive signal v gs1 of switch S 1 , the output voltages v o1 and v o2 are kept constant under different input voltages v i1 . And with the increase in v i1 , both D 1 and D 2 decrease, which effectively verifies the analysis presented in Fig. 13(b). Besides, from Fig. 15, i L (t 1 ) is a little decreased and i L (t 4 ) is almost unchanged with the increase in v i1 . It also validates the correctness of Fig. 13(c). In addition, according to Fig. 16, the steady voltage stress v s1 and v Ds2 of S 1 and D s2 are always equal to V o1 , irrespective of the variation of the input voltage. On the other hand, the voltage , which are, respectively, decreased and increased with the increase in v i1 . It is noteworthy that the oscillation of v s1 , v Ds2 , v s3 , and v Ds3 during the interval when i L = 0 is caused by the resonance of the inductor L and the parasitic capacitors of semiconductor devices. Fig. 17 also depicts the measured efficiencies of the proposed converter at different input voltages v i1 . Because there are two conducting switches/diodes in only one stage while one switch/diode conducts in the rest two stages, the number of active semiconductor devices in the proposed converter is small. Therefore, low conduction losses are achieved, contributing to high efficiencies. In Fig. 17, the minimum efficiency is 0.919, and the maximum efficiency is 0.98. It is noteworthy that the practical efficiencies would be a little decreased with the consideration of the loss of drive circuits.
Likewise, experiment waveforms of the proposed converter in Fig. 11(a) working in CCM are also illustrated in Figs. 18-20, which are in well coincidence with the theoretical analysis. Unlike the discontinuous currents in DCM, the inductor current is continuous in CCM. Hence, the oscillation of v s1 , v Ds2 , v s3 , and v Ds3 would not appear, as shown in Fig. 20. However, because of the hard-switching operation of switches and the reverse-recovery process of diodes, spike turn-OFF/ON voltage and currents are incurred in Figs. 19 and 20.
Besides, the dynamic response under load variation in DCM and CCM are shown in Fig. 21(a) and (b), respectively. In DCM, the two outputs are independently controlled and thus the variation of i o1 /i o2 only has an influence on v o1 /v o2 . Also, the simulation results of dynamic response under input voltage variation in DCM are also shown in Fig. 22, which is similar Fig. 19. Experimental waveforms of inductor current i L , drain-tosource currents i s1 and i s3 , and diode current i    to two separate buck-boost and boost converters. On the other hand, severe cross-regulation problem exists in CCM that both v o1 and v o2 will be influenced with the change of either i o1 or i o2 . Hence, improved control strategies are urgently demanded to improve the dynamic performance in CCM. Finally, the photograph of the prototype circuit in DCM is also given in Fig. 23. In CCM, only the inductor L is different, and, thus, its photograph is not illustrated again.

V. CONCLUSION
In this article, a simple principle of deriving SI-MIMO topologies from typical buck, boost, buck-boost, and noninverting buck-boost converters with only three steps was revealed. And as an example, a family of SI-SIDO, SI-DISO, and SI-DIDO topologies was derived and demonstrated in detail. With the proposed principle and the obtained SI-MIMO topologies, more choices are available and then an optimum one can be selected out for an engineering application. In addition, a family of SI-SIDO boost converters were also taken as an example to be compared under input voltages V i1 = 18-30 V and output voltages V o1 = 60 V and V o2 = 24 V, and a preferred one with lower conduction losses was finally selected, analyzed, and validated experimentally.