Published August 17, 2017 | Version v1
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Design and Implementation of Low Power Testing Using Advanced Razor Based Processor

Creators

  • 1. Sethu Institute of Technology

Description

In order to cope up with the functional operation criteria, our work concentrate on the percentage of indefinite values in the tests performed. A low-power broadside test set is shown from a functional broadside set with the derivation of skewed load test cubes in BIST circuits The twin effect of programmable truncated multiplication and fault-tolerant Digital Signal Processing (DSP) design is put on to reduce voltage beyond critical timing level. Timing modulation properties of truncated multiplication are examined for the betterment of fault-tolerant designs, reducing error correction burden, and extending the system operating voltage range. The lower power test schemes along with the advanced Razor technique is implemented with the original Digital signal Processing. The only demerit is the degradation of the output SNR.

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References

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