The development of flexible integrated circuits based on thin-film transistors

The use of thin-film transistors in liquid-crystal display applications was commercialized about 30 years ago. The key advantages of thin-film transistor technologies compared with traditional silicon complementary metal–oxide–semiconductor(CMOS) transistors are their ability to be manufactured on large substrates at low-cost per unit area and at low processing temperatures, which allows them to be directly integrated onto a variety of flexible substrates. Here, I discuss the potential of thin-film transistor technologies in the development of low-cost, flexible integrated circuits for applications beyond flat-panel displays, including the Internet of Things and lightweight wearable electronics. Focusing on the relatively mature thin-film transistor technologies that are available in semiconductor fabrication plants today, the different technologies are evaluated in terms of their potential circuit applications and the implications they will have in the design of integrated circuits, from basic logic gates to more complex digital and analogue systems. I also discuss microprocessors and non-silicon, near-field communication tags that can communicate with smartphones, and I propose the concept of a Moore’s law for flexible electronics. This Perspective discusses the potential of thin-film transistor technologies in the development of low-cost, flexible integrated circuits, evaluating the more mature technologies available today in terms of their potential circuit applications and the implications they will have in the design of integrated circuits.

T hin-film transistors (TFTs) are currently the dominant technology for in-pixel switches and drivers in flat-panel displays. Trends in consumer electronics demand ever-higher display resolution and brightness, lower power consumption, and new features and form factors (such as curved and foldable displays). This drives TFT devices to deliver more complex functions than simply switching. For example, recent bezel-less displays delegate the task of row selection to TFT circuits integrated next to the pixel array. Such driver circuits comprise thousands of switches operating together -previously a job for silicon chips mounted around the display.
Beyond displays, how far can thin-film circuits go in terms of replacing silicon complementary metal-oxide-semiconductor (CMOS) chips? Fig. 1 illustrates the key advantages of thin-film circuits on flexible substrates. The circuits can be fabricated on large substrates, thereby creating very thin, lightweight and ultra-flexible electronics 1,2 . Folding, rolling or crumpling such flexible circuits is possible without destroying the electronic functionality. Because of these properties, a flexible TFT-based microprocessor 3 (Fig. 1d) or thin-film near-field communication (NFC) tag (Fig. 1e) can, for example, be integrated imperceptibly into any object. TFT technologies also have considerable potential for fabrication on ultrathin stretchable substrates 4 that can be made porous to create breathable devices for contact with skin. With these features, thin-film integrated circuits (ICs) could be a game-changer for wearable electronics. Ultrathin, conformable ICs in the form of a tattoo could be used to monitor vital body parameters, communicating these parameters directly to a patient's smartphone or a medical database.
In this Perspective, I discuss the potential of thin-film circuits on plastic substrates for the development of Internet of Things (IoT) and wearable applications. First I look at the different TFT technologies that can be realized on flexible substrates, and then discuss the impact TFT technology will have on circuit design at the level of digital logic gates and very-large-scale integration (VLSI) digital circuits. For the latter, I consider the use of thin-film ICs in the creation of low-cost radiofrequency identification (RFID) tags for everyday items. Flexible chips may initially be used to simply identify each item. Then, when the RFID chip is potentially replaced with a thinfilm NFC chip, standard smartphones and tablets equipped with NFC readers could identify objects and connect them to the cloud. Another advantage of thin-film IC technology is its potential to be combined with sensor or signage technology, thereby integrating more functionality into the objects, which is discussed in a section on analogue circuits. Finally, I will briefly examine the potential of silicon CMOS chip technology to be interfaced directly with TFT circuitry.

TFT technology
The development and optimization of transistor technologies are driven by four important figures of merit: area, cost, power and performance. Power and performance are application-specific parameters that tend to become more demanding as the application field evolves. Because TFTs are developed mainly for display-like applications, the drivers of technological evolution are the demand for higher resolution and brightness, which pushes transistors to increased density and semiconductor performance. This evolution is also beneficial for thin-film IC applications.
TFT technologies have the potential to be low-cost, owing to the simple process flow (that is, limited number of lithographical steps, compared with Si CMOS) and material choices. Typical channel lengths for TFT technologies are in the micrometre range. Currently, thin-film ICs are area-inefficient due to non-optimized design flows, including the fact that transistor architectures have not been optimized for ICs. For example, a CMOS IC layout based on digital standard cells comprises several metal layers dedicated to routing that are on top of the Si CMOS transistor layers. Standard TFT transistor architectures on the other hand have a limited number of metal layers available (Fig. 1f), as additional metal layers are not required for backplane applications. Interconnecting different standard cells for a TFT-based digital chip can only be realized by the metal layers already present in the TFT stack. Routing on top of such standard cells cannot be maximized, resulting in non-optimal area consumption for TFT-based digital chips.

Kris Myny
The use of thin-film transistors in liquid-crystal display applications was commercialized about 30 years ago. The key advantages of thin-film transistor technologies compared with traditional silicon complementary metal-oxide-semiconductor (CMOS) transistors are their ability to be manufactured on large substrates at low-cost per unit area and at low processing temperatures, which allows them to be directly integrated onto a variety of flexible substrates. Here, I discuss the potential of thin-film transistor technologies in the development of low-cost, flexible integrated circuits for applications beyond flat-panel displays, including the Internet of Things and lightweight wearable electronics. Focusing on the relatively mature thin-film transistor technologies that are available in semiconductor fabrication plants today, the different technologies are evaluated in terms of their potential circuit applications and the implications they will have in the design of integrated circuits, from basic logic gates to more complex digital and analogue systems. I also discuss microprocessors and non-silicon, near-field communication tags that can communicate with smartphones, and I propose the concept of a Moore's law for flexible electronics.

Nature electroNics
At present, the mainstream TFT technologies available in consumer electronics products are amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS) and amorphous metal-oxide semiconductors (mainly indium-gallium-zinc-oxide, IGZO) ( Table 1). Metal-oxide TFT is a promising n-type-only technology for flexible IC circuits, as it can be manufactured at process temperatures within the thermal budget of flexible substrates 5 , while still exhibiting a charge carrier mobility close to or above 10 cm 2 V -1 s -1 , in contrast with 0.5-1 cm 2 V -1 s -1 for a-Si (refs 6,7 ). LTPS transistors require larger process temperatures and a more complex process flow, resulting in complementary p-type and n-type TFTs with larger mobilities (50-100 cm 2 V -1 s -1 ) 7,8 . In addition, the amorphous nature of IGZO as a semiconductor 5 provides a TFT scaling roadmap in which shorter-channel TFTs retain good performance characteristics, which is beneficial for both high-resolution displays and flexible IC applications. In contrast, polycrystalline semiconductors have a negative impact on TFT behaviour depending on the crystal size and channel length. IGZO TFTs with channels as short as 30 nm have already been demonstrated for transistors fabricated in the back-end-of-line of conventional silicon CMOS chip technology 9 . Moreover, organic transistors are widely studied as a potential candidate for flexible ICs to complement n-type metal-oxide TFTs 10 , because p-type metal-oxides matching the performance of amorphous IGZO have not yet been discovered.
A recent review of the effects of mechanical stress on the intrinsic electrical performance of different semiconductors concluded that amorphous metal-oxide semiconductors are the most resilient under mechanical strain 11 . In addition, semiconductors are patterned mostly into small islands and the critical layers of the TFT stack can be located near the neutral plane of the full stack by matching the substrate and the topstrate or encapsulation. This is fully exemplified by the ultra-flexible organic TFT backplane, which has a total thickness of just 2 μ m (ref. 1 ).
This Perspective focuses on the mature technologies that are available in semiconductor fabrication plants ('fabs') today. It is also worth noting a number of encouraging recent developments with carbon nanotubes [12][13][14][15] and several two-dimensional semiconductors 16 , such as graphene 15,17,18 , black phosphorus 19 and chalcogenides [20][21][22][23] , which could provide next-generation flexible TFT IC technologies, either as novel standalone transistor technologies or by complementing existing TFTs. Furthermore, a key benefit of some TFT technologies is the possibility to use additive manufacturing techniques like printing, which could reduce costs [24][25][26][27][28][29] . The main challenges of printed electronics at the circuit level are variability (device mismatch), large overlaps (source-drain to gate) due to layer-to-layer registration rules increasing the parasitics, and large device dimensions, which result in slower-operating circuits.

Digital logic gates
Logic gates are the building blocks of complex digital circuits and require specific optimization depending on the process technology. The most optimal configuration is CMOS, which profits from not only the co-existence of complementary p-type and n-type transistors, but also all the circuit techniques developed for conventional Si CMOS since the 1970s. Complementary logic is possible in LTPS, but organic and metal-oxide TFTs do not have adequate

PersPective
Nature electroNics complementary counterparts. The level of matching for both transistor types will affect the properties of the complementary logic gate, including speed, power, robustness and area. In a complementary technology, both transistor types must possess a near-zero threshold voltage and sufficiently low off-current. Furthermore, the charge carrier mobilities must differ by no more than a decade for both transisitor types. Low threshold voltages are essential for downscaling the supply voltage. Off-currents directly impact the static leakage current of a logic gate in both its on-and off-state, and therefore affect its total power consumption. Figure 2 shows an example whereby the off-current of the p-type transistor contributes mainly to the static power consumption for different integration levels of the targeted circuit. Low off-currents will become more important as we reach higher circuit integration densities. In addition, differences in charge carrier mobility between n-and p-type TFTs have an impact on area, speed and power. If the mobilities differ too much, the area consumption and speed of the complementary logic gate will be negatively affected in favour of unipolar logic gates. Implementing a complementary technology flow is more complex than fabricating a unipolar transistor technology, and the additional steps for a complementary flow relate directly to higher manufacturing cost. Therefore, from the cost perspective, unipolar technologies can be beneficial for the realization of a flexible digital IC, especially when there is no area reduction as a result of the introduction of a non-matching complementary semiconductor.
Unipolar logic gates are the main option for realizing flexible ICs in TFT technologies that do not have a complementary counterpart. The main disadvantages of unipolar logic gates over complementary logic gates are reduced robustness 30 and increased area and power consumption. Figure 2 details different unipolar logic topologies. Resistive-load logic requires on-chip resistors and will result in the lowest TFT count. If the technology does not offer resistors in the right range, a TFT can alternatively be used as a load. Two options in this regard are shown in Fig. 2e,f: enhancement-load or diodeload logic, and depletion-load or zero-V GS -load logic (V GS being the voltage between the gate and the source). The suitability of each option depends on the available threshold voltage of the existing technology. Zero-V GS -load logic only operates with normally-on devices, or devices that are already switched on at 0 V gate bias.
Diode-load logic operates much faster than zero-V GS -load logic but suffers from a low gain and reduced noise margin, and therefore lower overall robustness 31 .
Several methods can be used to increase the robustness of these logic gates. One option is to increase the number of transistors per logic gate in order to improve the noise margin, but at the cost of a larger area. Alternatively, transistors can be operated in two different operation modes -depletion or enhancement -and with at least two different threshold voltages per logic gate. The practicalities of implementing different threshold voltages are often dependent on the particular technology; examples include doping the channel, varying the thickness of the semiconductor and changing the gate-dielectric thickness. A primary consideration in the choice of the implementation is for process flow to stay sufficiently simple such that yield and cost remain attractive.
By nature of having a thin film of semiconductor as the active layer, a TFT can naturally be equipped with two gates: a front gate and a back gate. A back gate operates in a similar way to the body bias of Si CMOS and can therefore be used to regulate the threshold voltage of each TFT individually. Dual-gate unipolar inverters have already proven their benefits in terms of logic gate robustness 32 without an additional penalty on area. In this solution, a global chip-level bias signal is required, for example, to shift the threshold voltage V T for all drive TFTs. The inverter scheme is shown in Fig. 2g.
Logic gate robustness can also be improved for back-gatefree TFT technologies by introducing more transistors per logic gate. Two examples are level shifters 33 and pseudo-CMOS logic ( Fig. 2h) 34 , both of which shift the inverter's voltage transfer curve towards the middle of the power rail, thereby improving robustness. Besides an increase in consumed area, an additional power rail to drive the additional TFTs may be required for optimal operation. Level shifter logic with positive feedback employs 4-5 TFTs for an inverter function with only two power supplies 35 . This logic style results in the largest unipolar inverter gain and therefore the highest noise margin per supply voltage published to date (76 dB and 8.2 V on 20 V, respectively), which is obtained by positive feedback on the back-gate, including a global signal within power rails to tune individual threshold voltages. Finally, the robustness of unipolar logic gates can be improved by using unipolar differential logic, at  36 . This style uses only unipolar single-gate TFTs and combines positive feedback with the concept of differential logic. A fundamental problem of unipolar logic gates is their static power consumption. Dynamic logic is therefore an interesting area of research as it has already been shown to lower the static leakage current and reduce area consumption 37 . The leakage current of the technology has an impact on its operating frequency. VLSI TFT circuits based on such clocked dynamic logic are still a challenge because of the difficult design and strong requirements on clock synchronization.
Future trends may be to invent novel logic gates based on unipolar technologies that actively compensate for the shortcomings of regular unipolar logic gates, without needing to add the complementary transistor-type and, consequently, avoiding a more complex process flow. Such logic gates may employ additional transistors with a feedback function that reduces transistor leakage after the switching action has occurred 38 . Feedback circuits at the system level for disabling large idle blocks are also unexplored in TFT circuits.
A third way to lower the power consumption could be found in technological improvements or evolutionary steps. Technology scaling similar to Moore's law for flexible thin-film ICs may also be crucial for the realization of complex VLSI circuits on foil, thereby paving the way to a larger portfolio of applications. The intrinsic delay of scaled logic gates will improve with the scaling factor when full scaling (that is, equal in voltage and geometry) is applied (Fig. 2c). The transistor density needed to realize complex circuits improves with the square of the scaling factor, as does the power per function. The power density therefore remains equal. The NFC chip described in the following section is comprised of 1,712 metal-oxide n-TFTs, exhibiting 7.37 ns gate delay and 7.5 mW power consumption. Figure 2c recalculates this for 10,000 TFTs, assuming mainly static power losses. Applying Moore's law to flexible eletronics towards a 200 nm gate length results in 737 ps gate delay and 438 μ W power consumption for 10,000 n-TFTs. These numbers only consider advancements in the device parameters. In reality, parasitics from the interconnects play a crucial role and must be taken into account. Lowly resistive and strongly decoupled metal wires for interconnects are also of high importance for realizing this  46 . The red dashed line shows the impact on power and gate delay for the scaled-SAL NFC chip, if Moore's law for flexible electronics is applied with full geometry and voltage scaling, ranging from 5 μ m to 200 nm. The blue square is an extrapolation target that reveals the need for additional circuit and technology evolutions to reach ultralow-power, fast-operating circuits. d, n-type resistive-load logic. GND, ground. e, n-type diode-load logic. f, n-type zero-V GS -load logic. g, Dual-gate n-type diode-load logic. h, n-type diodeload pseudo-CMOS logic.

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roadmap. Power density will be of huge importance in the future, as circuits tend to evolve into more complex chips, yielding more functionality and transistors in a similar area. Power consumption and joule heating will require particular attention in thin-film technologies because plastic substrates and thin-film metals are poor heat conductors. If dynamic power consumption in such novel logic styles proves to be dominant, additional voltage scaling and clock frequency reductions (such as parallelism or pipelining) may contribute to lowering the overall power consumption. Other wellknown techniques such as optimal device sizing, clock gating and utilization of different logic styles in a single chip (fast logic gates versus low-power logic gates) can be explored for VLSI flexible ICs. TFT technologies are expected to improve parameters such as charge carrier mobility, variability and bias instability. Larger mobilities will enable logic gate optimization in terms of speed, area or a combination of both. With LTPS and amorphous oxide TFTs, the state-of-the-art transistor has a self-aligned architecture with minimum parasitic overlap between gate and source/drain 8,39-41 , thus providing fast logic gates with low power consumption. Figure 2c shows such an improvement in power consumption and gate delay for slower etch stopper layer (ESL) and faster self-aligned layer (SAL) metal-oxide TFT technologies. Figure 1f details the cross-section of both TFT architectures. ESL transistors exhibit a large parasitic gate-source and gate-drain overlap capacitor, which is substantially minimized for the SAL architecture. In addition, the channel length of SAL technology is equal to the definition of the gate layer, which makes it easily scalable, whereas the channel length of ESL technology is approximately three times its critical dimension due to the overlaps created by including the channel protection layer (as indicated in Fig. 1f). Further evolutions in stack definition are expected to provide more metallization layers for interconnects and additional downscaling of the transistor footprint.

Towards Vlsi (digital) circuits on foil
RFID tags have received significant attention in the field of thinfilm electronics because they could act as low-cost IoT nodes or be capable of tagging everyday objects. High-frequency RFID tags, operating at a base carrier frequency of 13.56 MHz, function at a maximum distance of 10 cm for proximity readers and up to 1 m for vicinity readers. TFT-based RFID tags can be grouped into two categories: those that communicate with specially designed RFID readers with custom protocols, like 8-, 12-or 16-bit tags [41][42][43][44][45] ; and those that communicate with commercial NFC readers, which are embedded in many smartphones and handheld devices. Chip design requirements are less stringent for the first category, as simpler protocols can be defined to account for the technology limitations of TFTs. Such protocols are embedded on small-sized dedicated chips with a limited number of transistors (< 1,000), which is less interesting for Si CMOS technologies.
NFC tags must comply with ISO standards (for example, ISO 14443-A), which were set for Si CMOS technologies exhibiting charge carrier mobilities approximately 100 times larger than those of metal-oxide TFTs. The selected ISO standard is the NFC barcode protocol, a tag-talks-only protocol whereby the tag transmits its 128-bit memory in 1.21 ms and remains silent for 3.6 ms. This fast NFC protocol can detect a tag within 5 ms. The three main challenges when designing a metal-oxide TFT-based NFC barcode tag are the data rates of 106 kbit s -1 (carrier frequency divided by 128), a 128-bit memory read-out, including 16 CRC bits, and a limited incident power at the tag from the smartphone, in the range of ~10 mW. The technology for this work is a self-aligned metal-oxide TFT architecture, which was selected because of its low parasitics and potential for downscaling the channel length to 2 μ m and 1.5 μ m (Fig. 1f). Pseudo-CMOS logic gates have been chosen to serve as the primary logic family for this technology, maintaining the robustness of the chip without the presence of a back-gate. Different implementations of the pseudo-CMOS logic gate have been used across the design to serve a variety of different purposes, including fast implementations for the clock division part and low-power implementations for the core part. Figure 3 depicts the effect of downscaling the channel length. The gate delay of a pseudo-CMOS inverter at 5 V V DD and 10 V V bias improves from 63.4 ns to 5.2 ns for 5 μ m to 2 μ m channel lengths. This is within the specified duration of 7.37 ns, determined as the maximum gate delay needed to directly divide the 13.56 MHz incoming clock signal. A fast pseudo-CMOS implementation with a 1.5 μ m channel length (L1.5F) results in a gate delay of 2.4 ns at 5 V V DD and 10 V V bias .
These gate delays are sufficient to divide the 13.56 MHz carrier frequency, yet the corresponding power figures suggest limiting the use of these gates when designing the full chip. Four different ratios yielding low-power pseudo-CMOS implementations have been evaluated, resulting in lower-power operation with a small increase in gate delay (Fig. 3c,d), which is affordable for the core part of the chip. Another key advantage of low-power implementations, particularly LP3 and LP4, is the more symmetric power distribution between V DD and V bias (Fig. 3g). This ensures the correct generation of V DD and V bias by the rectifier circuit, as both power nodes observe a similar load.
Low-power optimizations at the system and architectural levels have been performed by selectively choosing the proper pseudo-CMOS implementation where needed. The clock generator is a seven-stage toggle flip-flop chain in which the first stage is implemented with L1.5F logic (Fig. 4b). The power consumption has been decreased gradually along these seven stages by selecting slower and lower-power pseudo-CMOS gates. The final stages are implemented with LP3 at a channel length of 4 μ m, which has also been used for the digital core part (Fig. 4c). The data-formatting block requires a slightly faster operating speed; therefore LP3 at a channel length of 2 μ m has been selected. The CRC code is hardwired or pre-programmed in the memory because a regular CRC generator would add an additional 1/3 of the total number of TFTs, resulting in a substantial reduction in static power consumption. The memory has been realized in two generations: synthesized read-only memory (ROM), and laser-programmed ROM (LPROM). In LPROM, 16 bits of the payload and 16 CRC bits are one-time-programmable. Figure 4h shows the die picture of the combined clock generator, digital core generator and data-formatting block. The size of the final chip is determined by the geometry of the standard cell library and the number of metals used for interconnects, in this work limited to two, which also serve as gate and source-drain layer. An example standard cell is a two-input NOR gate (Fig. 4d) employing six IGZO TFTs and measuring 163 μ m × 290 μ m. The die picture of the chip also reveals the location of the standard cells and the gaps in between the cells for the automatic place and route algorithm. The efficiency of the routing -and therefore the chip downsizing -can be envisioned by introducing more routing layers, as discussed previously. The standard cell library consists of six cells, including a buffer and a flip-flop. Because automatic place and routing algorithms introduce more parasitics, it was decided to manually route the most time-critical blocks, such as the clock generator and the data-formatting block.
The final chip operates successfully at 3 V supply and 6 V V bias , consumes only 7.5 mW for 1,712 n-TFTs, and measures 50.55 mm 2 (Fig. 4e) 46 . Figure 1e shows a flexible NFC barcode chip, including rectifier and load modulator, combined with an inductive antenna. The chip also serves as the bridge that connects the antenna. The pre-programmed 128-bit memory on the flexible NFC tag can be successfully tapped wirelessly into an NFC-enabled smartphone. Figure 4e-g provides more measurement details and shows the chip's change in power with supply voltage. In addition, the mea-PersPective Nature electroNics sured signals of the IGZO NFC barcode tag when approached by an NFC reader device are plotted in Fig. 4f,g. The correct protocol behaviour is observed, with a silent period of 3.6 ms alternating between 1.21 ms code-transmission periods. A more detailed zoom of the first bits in the sequence shows the correct bit representation and bit-timing according to the ISO 14443-A protocol.
Another interesting and complex digital circuit is a microprocessor. The first (and so far most complex) thin-film flexible microprocessor was published in 2005 3 . It comprises ~32,000 transistors based on flexible complementary LTPS transistors, which are released from the carrier by employing the 'surface-free technology by laser ablation/annealing' process flow 47 . The first unipolar organic microprocessor fabricated directly on flexible substrates exhibited a clock frequency of 40 Hz to execute 8-bit operations 48 . In addition, 1-bit scalable microprocessor architectures have been demonstrated based on different emerging foil-compatible semiconductors, namely carbon nanotubes 12 and two-dimensional materials 49 . Solution-processed n-type metaloxides have been combined with an evaporated p-type organic semiconductor, resulting in the first hybrid organic-oxide 8-bit complementary thin-film microprocessors, operating at 2.1 kHz (ref. 10 ). Extrapolating the speed of the microprocessor by replacing the logic gates with aforementioned fast pseudo-CMOS logic gates may result in speeds of more than 100,000 instructions per second, thereby enabling a broad window of applications. The power consumption of this chip will probably exceed the application specifications, suggesting there is a strong need to apply techniques to reduce the power consumption. At the system level, disabling idle blocks in the architecture during operation by power gating, clock gating or active feedback via the back-gates can reduce power consumption. Designing complex architectures specifically for each application will also provide significant benefits. Unused gates should be eliminated 50 , memory and bus widths should be sized compliant to the application requirements, and VLSI circuit overheads should be limited. If sufficiently fast data processing can be brought to foil at low area and power consumption, a large application field can be envisioned whereby data is pre-processed at the patch or IoT-node level.

analogue circuits
IoT sensor nodes collect data in the analogue domain, to be digitized with analogue-to-digital or time-to-digital converters prior to cloud storage. Data processing in the digital domain is advantageous for TFT-based circuits, as digital circuits are more mature than analogue TFT-circuits. Analogue-to-digital converters have already been demonstrated in TFT technologies, based on a-Si, organic, metal-oxide and LTPS transistors, yielding up to 8-bit conversion at a maximum sampling rate of 300 S s -1 for unipolar IGZO technologies 51 . Many improvements are still required before commercial products are feasible, including a gradual change in process from 1-bit threshold sensing to multibit sensor conversion.
The analogue TFT world also benefits from the technological evolutions discussed in the previous section. Introducing higher-mobility semiconductors will lead to faster sampling rates and larger transconductances, assuming other TFT and process parameters remain similar. The conversion speed can be increased by downscaling the TFT technology, although the already limited gain of the operational amplifier or comparator may be reduced further owing to the lower output resistance of scaled TFTs. Improvements in variability and bias instability will lead to lower offset for differential amplifiers, thereby increasing the conversion accuracy. The introduction of a matching complementary TFT is likely to be the most significant development for analogue electronics, more so than introducing digital flexible ICs, improving conversion rates, strongly enhancing the offset and gain of the amplifiers, and downscaling the consumed area. Analogue circuits based on unipolar technologies already benefit if stable passives (such as a high-resistivity layer with low variation) are included in the process flow, thereby improving the area and gain of the amplifiers.

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Amplifiers are required for a multitude of applications, not only sensor-node IoT. Integrated sense amplifiers are beneficial for reading out different memory topologies in a rapid fashion, from LPROM to static random-access memory 52 , and in future could be used in non-volatile memory arrays embedded in TFT technologies. Large-area imaging backplanes require in-pixel

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amplification and sense amplifiers to detect incoming signals. Low-noise amplification based on TFT technologies could also be used in wearable health patches to monitor vital signals, wherein sensors or electrodes are attached to the body and interconnected to a Si CMOS IC. The analogue amplifiers can be mounted nearby the sensor/electrode to improve the signal-tonoise ratio of the sensor signal prior to transmission to the Si IC. Single-stage high-gain amplification in such patches is a strong asset that has been demonstrated by means of a positive feedback mechanism and back-gate technology in a unipolar IGZObased design, leading to 30 dB gain 53 . The back-gate is capable of not only enabling multi-threshold voltage logic (as discussed earlier), but also improving the transconductance or the output resistance of the individual transistors. Enhancing these TFT parameters is a valuable property of analogue circuits, which consists of load TFTs and current sources that require a large output resistance, or improved transconductance for the input pairs, leading to 50 dB gain for a three-stage unipolar metaloxide amplifier 54 .
Designing analogue electronics requires a key understanding of the mismatch or deviations of parameters between two transistors. A mismatch law for conventional Si CMOS has been reported 55 , in which it was concluded that device parameter mismatch is inversely proportional to the square root of the device area. A properly operating differential input pair or a current-mirror circuit relies on the matching properties of two transistors. It has been shown that the spread in organic transistor characteristics is too large, thereby excluding the design of a current-steering digital-to-analogue conversion architecture 56 . Instead, for this organic technology, it was found that the capacitor mismatch follows Pelgrom's area-scaling rule, resulting in a 6-bit switched-capacitor architecture. An interesting post-fabrication select-and-connect method has also been reported to cope with large mismatch values for organic transistors 57 . This method led to an optimal area and power overhead reduction, compared with the introduction of many parallel transistors. Device mismatch is a problem not only during manufacturing (for dimensions, doping and interfaces), but also during handling and operation. Mechanical handling of flexible electronics can introduce locally tensile or compressive stress on the device and therefore impact its characteristics. A proper 'floor plan' of the design is required to accommodate for such effects in final product handling. During operation, two transistors in a differential pair may be biased with different conditions, resulting in a different reduction in bias stress current for each transistor. This causes the device characteristics to start deviating, which impacts the proper functioning of the differential pair. It will be important for future developments, as technologies mature, to obtain accurate models of the transistor behaviour under different circumstances, thereby ensuring correct functioning of the analogue blocks without severe design overhead.
Combining health patches or sensor nodes with RFID or NFC tags is an intriguing direction for this field. As explained previously, an accurate and stable time signal can be derived from the incoming carrier frequency in an RFID tag. This time reference can be used to convert the sensor signal to a digital value via a time-to-digital converter. A full NFC solution based on the NFC barcode protocol sets restrictions for the data conversion rate, as 128-bit data is transmitted within 1.21 ms. The minimum time for analogue conversion is around 1 ms, depending on the number of occurrences needed prior to smartphone detection. Afterwards, the converted digital bit sequence must be included together with a newly calculated 16-bit CRC number, albeit by means of a CRC generator, a look up table or a synthesized code scheme. The number of converter bits will decide which of the previously discussed solutions may be the most appropriate, given the area and power constraints of the tag.

Hybrid combination of silicon cMos and TFT technologies
There are number of potential opportunities for Si CMOS chip technology to be interfaced directly with TFT circuitry. I focus here on solutions in which there is a clear gap in system requirements and solutions offered by specific IC technologies. Flexible TFTs are limited mainly in terms of their electrical performance; for example, Bluetooth or WiFi communication with TFTs is not yet possible due to the limited cut-off frequency. Si CMOS ICs, in contrast, have area constraints and are therefore limited in terms of their number of input/output pads. Thus, it would be beneficial in some cases to combine silicon CMOS ICs and TFT flexible chips at the system level. The choice for this solution will be strongly dependent on the system requirements and will affect the cost and complexity of the solution. An example of such integration is the hybrid system-infoil approach 58,59 , in which a thinned silicon CMOS IC is embedded in a flexible substrate and combined with foil-compatible TFT technologies and sensors. Previous sections discussed some examples of this approach, such as a Si NFC reader chip wirelessly connecting to a flexible TFT-based NFC tag, or a TFT low-noise amplifier located near a sensor input to improve the signal-to-noise ratio prior to transmitting this analogue signal to a Si chip. More obvious examples are in fact active matrix displays and imagers. A TFT backplane in a display uses its transistors solely as switches or to regulate the current through the OLED frontplane. More advanced pixel schemes also employ multiple TFTs per pixel, thereby compensating for the non-idealities of TFT backplanes, such as bias instabilities and uniformity issues. Si CMOS chips, like a graphics processing unit, will translate the display image into the desired data and then select signals. The trend towards bezel-free displays moves more complexity to the TFT backplanes, requiring integrating TFT-based scan drivers for the signal selection and multiplexers to reduce the number of data control signals.
A multiplexer/demultiplexer circuit based on TFTs could be valuable for actively extending the limited number of input/output pins of a Si CMOS chip. Applications that require a large number of sensors or actuators can be envisioned in this regard. A largearea wearable patch could consist of a large array of distributed electrodes, with a TFT-based amplifier or analogue-to-digital converter attached to each electrode. The pre-treated signals are subsequently transmitted to a single Si CMOS IC by means of a TFT-based multiplexer, for which time-or frequency-division multiplexing of the input/output pins are two valid candidates. The bandwidth of the multiplexer will depend strongly on the technology, voltage range, number of input/output pins and power budget. Downscaling TFT technologies will lead to lower supply voltages; 5 V, 3.3 V, 1.5 V and sub-1 V V DD voltages can be envisioned, enabling direct communication between a flexible TFT IC and a Si CMOS IC 60 . On the other hand, Si CMOS ICs that need to drive high voltage actuators can make use of TFT-based level shifters to increase the CMOScompatible voltage range towards that required by the actuator.

conclusions
This Perspective discussed the opportunities and shortcomings of TFT technologies for applications beyond displays, such as low-cost IoT and wearable electronics. In order to optimize cost, robustness, area and power, improvements in transistor technology must be driven by the needs of flexible TFT-based ICs. One circuit-specific technology improvement includes the introduction of Moore's law for flexible electronics, in which flexible chips may become smaller, thinner and higher performing. Another key asset for TFT technologies is an individual back-gate for each transistor, which can be employed in logic gates to enable the use of multiple threshold voltages and therefore provide more robust digital logic, or in analogue circuits where the transconductance or output resistance must be adapted. Complex routing in flexible circuit technology may also require extra metal layers in addition to the gate and source-drain Nature electroNics layer, which may improve the circuit's power consumption, speed and area usage. Unipolar logic circuits have clear advantages over complementary logic gates in terms of a simpler process flow and therefore lower costs, which is an important aspect for these technologies.
Technology-aware design improvements are also necessary to bridge the shortcomings of TFT technologies. Several TFT technologies are limited to only unipolar semiconductors; various implementations of unipolar logic gates have improved the robustness, dynamic performance and power consumption of such devices. This has been realized by employing more transistors per logic gate, or by actively implementing the back-gate. In the future, more dedicated improvements regarding this topic are required to enable applications that require more complex flexible ICs with a higher integration density, operating within the power and speed budgets of the applications. A complementary approach that combines nand p-type TFTs may result in more complex manufacturing processes, but has great advantages in terms of circuit performance. Different transistor technologies, like two-dimensional materials or carbon nanotubes, could be integrated with unipolar TFT technologies to enable favourable complementary logic. Complex digital and analogue TFT circuits have already been demonstrated, from RFID tags and analogue-to-digital converters to flexible microprocessors, which indicates the readiness of TFT technologies for such applications. A TFT-based unipolar NFC tag has been discussed in which power consumption and speed has been optimized at the logic-gate and system level. This leads to a 7.5 mW IGZO-based NFC tag that can tap its information directly into an NFC-enabled smartphone. Such an ultrathin tag could be invisibly embedded into everyday objects, thereby enabling the development of item-level IoT nodes.