Poster Open Access

A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder

Sezer, E. Göksu; Arikan, Erdal

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<oai_dc:dc xmlns:dc="" xmlns:oai_dc="" xmlns:xsi="" xsi:schemaLocation="">
  <dc:creator>Sezer, E. Göksu</dc:creator>
  <dc:creator>Arikan, Erdal</dc:creator>
  <dc:description>It is foreseen that for some of the beyond-5G applications, there will be demand for data rates up to 1 Tb/s [1]. Polar codes, introduced in [2], is one of the leading code classes for beyond-5G applications for reaching mentioned high throughputs with limited area and power consumption. Therefore polar code implementations, especially successive cancellation (SC), to reach high data rates is frequently studied subject. This study uses the successive cancellation list decoding [3] (SCL) polar decoder for list length equal to 2. The decoder is implemented on Xilinx Virtex-7 Ultrascale+FPGA available on the Amazon Web Services. Results of our study yields promising results towards reaching high throughput values within the EPIC project limits when the results are scaled to 7nm ASIC.</dc:description>
  <dc:subject>Polar Codes</dc:subject>
  <dc:title>A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder</dc:title>
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