Poster Open Access

A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder

Sezer, E. Göksu; Arikan, Erdal


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    "description": "<p>It is foreseen that for some of the beyond-5G&nbsp;applications, there will be demand for data rates up to 1&nbsp;Tb/s [1]. Polar codes, introduced in [2], is one of the&nbsp;leading code classes for beyond-5G applications for&nbsp;reaching mentioned high throughputs with limited area&nbsp;and power consumption. Therefore polar code&nbsp;implementations, especially successive cancellation (SC),&nbsp;to reach high data rates is frequently studied subject.&nbsp;This study uses the successive cancellation list decoding&nbsp;[3] (SCL) polar decoder for list length equal to 2. The&nbsp;decoder is implemented on Xilinx Virtex-7 Ultrascale+FPGA available on the Amazon Web Services. Results of&nbsp;our study yields promising results towards reaching high&nbsp;throughput values within the EPIC project limits when the&nbsp;results are scaled to 7nm ASIC.</p>", 
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    "title": "A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder", 
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    "keywords": [
      "Polar Codes"
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    "publication_date": "2019-12-06", 
    "creators": [
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        "affiliation": "Polaran Ltd.", 
        "name": "Sezer, E. G\u00f6ksu"
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        "affiliation": "Polaran Ltd.", 
        "name": "Arikan, Erdal"
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