10.5281/zenodo.3565305
https://zenodo.org/records/3565305
oai:zenodo.org:3565305
Sezer, E. Göksu
E. Göksu
Sezer
Polaran Ltd.
Arikan, Erdal
Erdal
Arikan
Polaran Ltd.
A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder
Zenodo
2019
Polar Codes
2019-12-06
Poster
10.5281/zenodo.3565304
https://zenodo.org/communities/epic_h2020
https://zenodo.org/communities/eu
Creative Commons Attribution 4.0 International
It is foreseen that for some of the beyond-5G applications, there will be demand for data rates up to 1 Tb/s [1]. Polar codes, introduced in [2], is one of the leading code classes for beyond-5G applications for reaching mentioned high throughputs with limited area and power consumption. Therefore polar code implementations, especially successive cancellation (SC), to reach high data rates is frequently studied subject. This study uses the successive cancellation list decoding [3] (SCL) polar decoder for list length equal to 2. The decoder is implemented on Xilinx Virtex-7 Ultrascale+FPGA available on the Amazon Web Services. Results of our study yields promising results towards reaching high throughput values within the EPIC project limits when the results are scaled to 7nm ASIC.
European Commission
10.13039/501100000780
760150
Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding