Poster Open Access

A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder

Sezer, E. Göksu; Arikan, Erdal


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  <identifier identifierType="DOI">10.5281/zenodo.3565305</identifier>
  <creators>
    <creator>
      <creatorName>Sezer, E. Göksu</creatorName>
      <givenName>E. Göksu</givenName>
      <familyName>Sezer</familyName>
      <affiliation>Polaran Ltd.</affiliation>
    </creator>
    <creator>
      <creatorName>Arikan, Erdal</creatorName>
      <givenName>Erdal</givenName>
      <familyName>Arikan</familyName>
      <affiliation>Polaran Ltd.</affiliation>
    </creator>
  </creators>
  <titles>
    <title>A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2019</publicationYear>
  <subjects>
    <subject>Polar Codes</subject>
  </subjects>
  <dates>
    <date dateType="Issued">2019-12-06</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Poster</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/3565305</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsVersionOf">10.5281/zenodo.3565304</relatedIdentifier>
    <relatedIdentifier relatedIdentifierType="URL" relationType="IsPartOf">https://zenodo.org/communities/epic_h2020</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by/4.0/legalcode">Creative Commons Attribution 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;It is foreseen that for some of the beyond-5G&amp;nbsp;applications, there will be demand for data rates up to 1&amp;nbsp;Tb/s [1]. Polar codes, introduced in [2], is one of the&amp;nbsp;leading code classes for beyond-5G applications for&amp;nbsp;reaching mentioned high throughputs with limited area&amp;nbsp;and power consumption. Therefore polar code&amp;nbsp;implementations, especially successive cancellation (SC),&amp;nbsp;to reach high data rates is frequently studied subject.&amp;nbsp;This study uses the successive cancellation list decoding&amp;nbsp;[3] (SCL) polar decoder for list length equal to 2. The&amp;nbsp;decoder is implemented on Xilinx Virtex-7 Ultrascale+FPGA available on the Amazon Web Services. Results of&amp;nbsp;our study yields promising results towards reaching high&amp;nbsp;throughput values within the EPIC project limits when the&amp;nbsp;results are scaled to 7nm ASIC.&lt;/p&gt;</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/760150/">760150</awardNumber>
      <awardTitle>Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding</awardTitle>
    </fundingReference>
  </fundingReferences>
</resource>
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