Poster Open Access

A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder

Sezer, E. Göksu; Arikan, Erdal


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        <foaf:name>Sezer, E. Göksu</foaf:name>
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        <foaf:name>Arikan, Erdal</foaf:name>
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    <dct:title>A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder</dct:title>
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    <dct:issued rdf:datatype="http://www.w3.org/2001/XMLSchema#gYear">2019</dct:issued>
    <dcat:keyword>Polar Codes</dcat:keyword>
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    <dct:description>&lt;p&gt;It is foreseen that for some of the beyond-5G&amp;nbsp;applications, there will be demand for data rates up to 1&amp;nbsp;Tb/s [1]. Polar codes, introduced in [2], is one of the&amp;nbsp;leading code classes for beyond-5G applications for&amp;nbsp;reaching mentioned high throughputs with limited area&amp;nbsp;and power consumption. Therefore polar code&amp;nbsp;implementations, especially successive cancellation (SC),&amp;nbsp;to reach high data rates is frequently studied subject.&amp;nbsp;This study uses the successive cancellation list decoding&amp;nbsp;[3] (SCL) polar decoder for list length equal to 2. The&amp;nbsp;decoder is implemented on Xilinx Virtex-7 Ultrascale+FPGA available on the Amazon Web Services. Results of&amp;nbsp;our study yields promising results towards reaching high&amp;nbsp;throughput values within the EPIC project limits when the&amp;nbsp;results are scaled to 7nm ASIC.&lt;/p&gt;</dct:description>
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