Poster Open Access

A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder

Sezer, E. Göksu; Arikan, Erdal


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{
  "publisher": "Zenodo", 
  "DOI": "10.5281/zenodo.3565305", 
  "author": [
    {
      "family": "Sezer, E. G\u00f6ksu"
    }, 
    {
      "family": "Arikan, Erdal"
    }
  ], 
  "issued": {
    "date-parts": [
      [
        2019, 
        12, 
        6
      ]
    ]
  }, 
  "abstract": "<p>It is foreseen that for some of the beyond-5G&nbsp;applications, there will be demand for data rates up to 1&nbsp;Tb/s [1]. Polar codes, introduced in [2], is one of the&nbsp;leading code classes for beyond-5G applications for&nbsp;reaching mentioned high throughputs with limited area&nbsp;and power consumption. Therefore polar code&nbsp;implementations, especially successive cancellation (SC),&nbsp;to reach high data rates is frequently studied subject.&nbsp;This study uses the successive cancellation list decoding&nbsp;[3] (SCL) polar decoder for list length equal to 2. The&nbsp;decoder is implemented on Xilinx Virtex-7 Ultrascale+FPGA available on the Amazon Web Services. Results of&nbsp;our study yields promising results towards reaching high&nbsp;throughput values within the EPIC project limits when the&nbsp;results are scaled to 7nm ASIC.</p>", 
  "title": "A FPGA Implementation Study of Successive Cancellation List=2 Polar Decoder", 
  "type": "graphic", 
  "id": "3565305"
}
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