October 9, 2019 Conference paper Open Access

Süral, Altug; Sezer, Göksu; Ertugrul, Yigit; Arikan, Orhan; Arikan, Erdal

MARC21 XML Export

<?xml version='1.0' encoding='UTF-8'?>
<record xmlns="http://www.loc.gov/MARC21/slim">
  <leader>00000nam##2200000uu#4500</leader>
  <datafield tag="653" ind1=" " ind2=" ">
    <subfield code="a">Polar Codes</subfield>
  </datafield>
  <datafield tag="653" ind1=" " ind2=" ">
    <subfield code="a">Successive Cancellation - Majority Logic DECODING</subfield>
  </datafield>
  <controlfield tag="005">20200120172138.0</controlfield>
  <controlfield tag="001">3477875</controlfield>
  <datafield tag="711" ind1=" " ind2=" ">
    <subfield code="d">8-11 September 2019</subfield>
    <subfield code="g">IEEE pimrc</subfield>
    <subfield code="a">IEEE International Symposium on Personal, Indoor and Mobile Radio Communications</subfield>
    <subfield code="c">Istanbul</subfield>
  </datafield>
  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="u">POL</subfield>
    <subfield code="a">Sezer, Göksu</subfield>
  </datafield>
  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="u">POL</subfield>
    <subfield code="a">Ertugrul, Yigit</subfield>
  </datafield>
  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="u">POL</subfield>
    <subfield code="a">Arikan, Orhan</subfield>
  </datafield>
  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="u">POL</subfield>
    <subfield code="a">Arikan, Erdal</subfield>
  </datafield>
  <datafield tag="856" ind1="4" ind2=" ">
    <subfield code="s">603640</subfield>
    <subfield code="z">md5:133a9c42a41394f07724a620b68e80f9</subfield>
    <subfield code="u">https://zenodo.org/record/3477875/files/2019_POL_PIMRC_Paper.pdf</subfield>
  </datafield>
  <datafield tag="542" ind1=" " ind2=" ">
    <subfield code="l">open</subfield>
  </datafield>
  <datafield tag="260" ind1=" " ind2=" ">
    <subfield code="c">2019-10-09</subfield>
  </datafield>
  <datafield tag="909" ind1="C" ind2="O">
    <subfield code="p">openaire</subfield>
    <subfield code="p">user-epic_h2020</subfield>
    <subfield code="o">oai:zenodo.org:3477875</subfield>
  </datafield>
  <datafield tag="100" ind1=" " ind2=" ">
    <subfield code="u">POL</subfield>
    <subfield code="a">Süral, Altug</subfield>
  </datafield>
  <datafield tag="245" ind1=" " ind2=" ">
    <subfield code="a">Terabits-per-Second Throughput for Polar Codes</subfield>
  </datafield>
  <datafield tag="980" ind1=" " ind2=" ">
    <subfield code="a">user-epic_h2020</subfield>
  </datafield>
  <datafield tag="536" ind1=" " ind2=" ">
    <subfield code="c">760150</subfield>
    <subfield code="a">Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding</subfield>
  </datafield>
  <datafield tag="540" ind1=" " ind2=" ">
    <subfield code="u">https://creativecommons.org/licenses/by/4.0/legalcode</subfield>
    <subfield code="a">Creative Commons Attribution 4.0 International</subfield>
  </datafield>
  <datafield tag="650" ind1="1" ind2="7">
    <subfield code="a">cc-by</subfield>
    <subfield code="2">opendefinition.org</subfield>
  </datafield>
  <datafield tag="520" ind1=" " ind2=" ">
    <subfield code="a">&lt;p&gt;By using Majority Logic (MJL) aided Successive&amp;nbsp;Cancellation (SC) decoding algorithm, an architecture&amp;nbsp;and a specific implementation for high throughput polar&amp;nbsp;coding are proposed. SC-MJL algorithm exploits the low&amp;nbsp;complexity nature of SC decoding and the low latency&amp;nbsp;property of MJL. In order to reduce the complexity of&amp;nbsp;SC-MJL decoding, an adaptive quantization scheme is&amp;nbsp;developed within 1-5 bits range of internal log-likelihood&amp;nbsp;ratios (LLRs). The bit allocation is based on maximizing&amp;nbsp;the mutual information between the input and output&amp;nbsp;LLRs of the quantizer. This scheme causes a negligible&amp;nbsp;(0.1 &amp;lt; dB) performance loss when the code block length&amp;nbsp;is N = 1024 and the number of information bits is&amp;nbsp;K = 854. The decoder is implemented on 45nm ASIC&amp;nbsp;technology using deeply-pipelined, unrolled hardware architecture&amp;nbsp;with register balancing. The pipeline depth is&amp;nbsp;kept at 40 clock cycles in ASIC by merging consecutive&amp;nbsp;decoding stages implemented as combinational logic. The&amp;nbsp;ASIC synthesis results show that SC-MJL decoder has&amp;nbsp;427 Gb/s throughput at 45nm technology. When we scale&amp;nbsp;the implementation results to 7nm technology node, the&amp;nbsp;throughput reaches 1 Tb/s with under 10 mm2 chip area&amp;nbsp;and 0.37 W power dissipation.&lt;/p&gt;</subfield>
  </datafield>
  <datafield tag="773" ind1=" " ind2=" ">
    <subfield code="n">doi</subfield>
    <subfield code="i">isVersionOf</subfield>
    <subfield code="a">10.5281/zenodo.3477874</subfield>
  </datafield>
  <datafield tag="024" ind1=" " ind2=" ">
    <subfield code="a">10.5281/zenodo.3477875</subfield>
    <subfield code="2">doi</subfield>
  </datafield>
  <datafield tag="980" ind1=" " ind2=" ">
    <subfield code="a">publication</subfield>
    <subfield code="b">conferencepaper</subfield>
  </datafield>
</record>