Conference paper Open Access

Terabits-per-Second Throughput for Polar Codes

Süral, Altug; Sezer, Göksu; Ertugrul, Yigit; Arikan, Orhan; Arikan, Erdal


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    <dct:title>Terabits-per-Second Throughput for Polar Codes</dct:title>
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    <dcat:keyword>Polar Codes</dcat:keyword>
    <dcat:keyword>Successive Cancellation - Majority Logic DECODING</dcat:keyword>
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    <dct:description>&lt;p&gt;By using Majority Logic (MJL) aided Successive&amp;nbsp;Cancellation (SC) decoding algorithm, an architecture&amp;nbsp;and a specific implementation for high throughput polar&amp;nbsp;coding are proposed. SC-MJL algorithm exploits the low&amp;nbsp;complexity nature of SC decoding and the low latency&amp;nbsp;property of MJL. In order to reduce the complexity of&amp;nbsp;SC-MJL decoding, an adaptive quantization scheme is&amp;nbsp;developed within 1-5 bits range of internal log-likelihood&amp;nbsp;ratios (LLRs). The bit allocation is based on maximizing&amp;nbsp;the mutual information between the input and output&amp;nbsp;LLRs of the quantizer. This scheme causes a negligible&amp;nbsp;(0.1 &amp;lt; dB) performance loss when the code block length&amp;nbsp;is N = 1024 and the number of information bits is&amp;nbsp;K = 854. The decoder is implemented on 45nm ASIC&amp;nbsp;technology using deeply-pipelined, unrolled hardware architecture&amp;nbsp;with register balancing. The pipeline depth is&amp;nbsp;kept at 40 clock cycles in ASIC by merging consecutive&amp;nbsp;decoding stages implemented as combinational logic. The&amp;nbsp;ASIC synthesis results show that SC-MJL decoder has&amp;nbsp;427 Gb/s throughput at 45nm technology. When we scale&amp;nbsp;the implementation results to 7nm technology node, the&amp;nbsp;throughput reaches 1 Tb/s with under 10 mm2 chip area&amp;nbsp;and 0.37 W power dissipation.&lt;/p&gt;</dct:description>
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