Conference paper Open Access

Terabits-per-Second Throughput for Polar Codes

Süral, Altug; Sezer, Göksu; Ertugrul, Yigit; Arikan, Orhan; Arikan, Erdal

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  "publisher": "Zenodo", 
  "DOI": "10.5281/zenodo.3477875", 
  "title": "Terabits-per-Second Throughput for Polar Codes", 
  "issued": {
    "date-parts": [
  "abstract": "<p>By using Majority Logic (MJL) aided Successive&nbsp;Cancellation (SC) decoding algorithm, an architecture&nbsp;and a specific implementation for high throughput polar&nbsp;coding are proposed. SC-MJL algorithm exploits the low&nbsp;complexity nature of SC decoding and the low latency&nbsp;property of MJL. In order to reduce the complexity of&nbsp;SC-MJL decoding, an adaptive quantization scheme is&nbsp;developed within 1-5 bits range of internal log-likelihood&nbsp;ratios (LLRs). The bit allocation is based on maximizing&nbsp;the mutual information between the input and output&nbsp;LLRs of the quantizer. This scheme causes a negligible&nbsp;(0.1 &lt; dB) performance loss when the code block length&nbsp;is N = 1024 and the number of information bits is&nbsp;K = 854. The decoder is implemented on 45nm ASIC&nbsp;technology using deeply-pipelined, unrolled hardware architecture&nbsp;with register balancing. The pipeline depth is&nbsp;kept at 40 clock cycles in ASIC by merging consecutive&nbsp;decoding stages implemented as combinational logic. The&nbsp;ASIC synthesis results show that SC-MJL decoder has&nbsp;427 Gb/s throughput at 45nm technology. When we scale&nbsp;the implementation results to 7nm technology node, the&nbsp;throughput reaches 1 Tb/s with under 10 mm2 chip area&nbsp;and 0.37 W power dissipation.</p>", 
  "author": [
      "family": "S\u00fcral, Altug"
      "family": "Sezer, G\u00f6ksu"
      "family": "Ertugrul, Yigit"
      "family": "Arikan, Orhan"
      "family": "Arikan, Erdal"
  "id": "3477875", 
  "event-place": "Istanbul", 
  "type": "paper-conference", 
  "event": "IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE pimrc)"
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