Journal article Open Access

In-the-Field Mitigation of Process Variability for Improved FPGA Performance

Maragos, Konstantinos; Lentaris, George; Soudris, Dimitrios

DataCite XML Export

<?xml version='1.0' encoding='utf-8'?>
<resource xmlns:xsi="" xmlns="" xsi:schemaLocation="">
  <identifier identifierType="URL"></identifier>
      <creatorName>Maragos, Konstantinos</creatorName>
      <affiliation>School of Electrical and Computer Engineering, National Technical University of Athens (NTUA)</affiliation>
      <creatorName>Lentaris, George</creatorName>
      <affiliation>School of Electrical and Computer Engineering, National Technical University of Athens (NTUA)</affiliation>
      <creatorName>Soudris, Dimitrios</creatorName>
      <affiliation>School of Electrical and Computer Engineering, National Technical University of Athens (NTUA)</affiliation>
    <title>In-the-Field Mitigation of Process Variability for Improved FPGA Performance</title>
    <date dateType="Issued">2019-02-12</date>
  <resourceType resourceTypeGeneral="JournalArticle"/>
    <alternateIdentifier alternateIdentifierType="url"></alternateIdentifier>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/TC.2019.2898833</relatedIdentifier>
    <rights rightsURI="">Creative Commons Attribution 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
    <description descriptionType="Abstract">&lt;p&gt;The mitigation of process variability becomes paramount as chip fabrication advances deeper into the sub-micron regime. Conservative guard-bands result in considerable performance loss, while most low-level solutions impede dynamic customization at application level. This paper exploits the existing process variability of commercial off-the-shelf FPGAs to improve the operating frequency of a design, in-the-field, at anytime during the lifetime of a chip. We begin by measuring variability in prevalent FPGAs and assessing its impact on the performance of common DSP benchmarks. For the former, we develop a custom sensing network of Ring-Oscillators to generate detailed 2D maps per chip. For the latter, we perform intensive testing and statistical analysis to establish the relation between variability maps and benchmark frequencies. Accordingly, we propose a framework to automatically characterize the user&amp;#39;s devices, place the design on the most efficient region, and scale its frequency based on user requirements and functional verification. Experimental results on 20 FPGAs of 28 nm Xilinx technology show up to 13 percent intra-die and 30 percent inter-die variability; with limited cost, our framework provides 10-14.7 percent average gain by exploiting such variability, or up to 56-138 percent by also customizing the guard-band.&lt;/p&gt;</description>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/780572/">780572</awardNumber>
      <awardTitle>Software Development toolKit for Energy optimization and technical Debt elimination</awardTitle>
Views 48
Downloads 111
Data volume 530.9 MB
Unique views 41
Unique downloads 108


Cite as