September 13, 2018 Conference paper Open Access

Riccardo Cantoro; Aleksa Damljanovic; Matteo Sonza Reorda; Giovanni Squillero

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  <identifier identifierType="URL">https://zenodo.org/record/3362596</identifier>
  <creators>
    <creator>
      <creatorName>Riccardo Cantoro</creatorName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Aleksa Damljanovic</creatorName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Matteo Sonza Reorda</creatorName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Giovanni Squillero</creatorName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
  </creators>
  <titles>
    <title>A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2018</publicationYear>
  <dates>
    <date dateType="Issued">2018-09-13</date>
  </dates>
  <language>en</language>
  <resourceType resourceTypeGeneral="ConferencePaper"/>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/3362596</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/ITC-Asia.2018.00020</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by/4.0/legalcode">Creative Commons Attribution 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;The broad need to efficiently access all the instrumentation embedded within a semiconductor device called for a standardization, and the reconfigurable scan networks proposed in IEEE 1687 have been demonstrated effective in handling complex infrastructures. At the same time, different techniques have been proposed to test the new circuitry required; however, most of the automatic approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper models the state of a reconfigurable scan network with a finite state automaton, using the length of the active path as the output alphabet and the configurations as input symbols. Permanent faults are represented as incorrect transitions, and a greedy algorithm is used to generate a functional test sequence able to detect all these multiple state-transition faults. The automaton&amp;#39;s state set and the input alphabet are small subsets of the possible ones, and are carefully chosen. Experimental results on ITC&amp;#39;16 benchmarks demonstrate that the proposed approach is broadly applicable; the test sequences are more efficient than the ones previously generated by search heuristics.&lt;/p&gt;</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/100010661</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/722325/">722325</awardNumber>
      <awardTitle>Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design</awardTitle>
    </fundingReference>
  </fundingReferences>
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