Conference paper Open Access

A Novel Error Rate Estimation Approach for UltraScale+ SRAM-based FPGAs

Sterpone, Luca; Azimi, Sarah; Bozzoli, Ludovica; Du, Boyang; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Polo, Cesar Boatella; Codinachs, David Merodio


DataCite XML Export

<?xml version='1.0' encoding='utf-8'?>
<resource xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://datacite.org/schema/kernel-4" xsi:schemaLocation="http://datacite.org/schema/kernel-4 http://schema.datacite.org/meta/kernel-4.1/metadata.xsd">
  <identifier identifierType="URL">https://zenodo.org/record/3362341</identifier>
  <creators>
    <creator>
      <creatorName>Sterpone, Luca</creatorName>
      <givenName>Luca</givenName>
      <familyName>Sterpone</familyName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Azimi, Sarah</creatorName>
      <givenName>Sarah</givenName>
      <familyName>Azimi</familyName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Bozzoli, Ludovica</creatorName>
      <givenName>Ludovica</givenName>
      <familyName>Bozzoli</familyName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Du, Boyang</creatorName>
      <givenName>Boyang</givenName>
      <familyName>Du</familyName>
      <affiliation>Politecnico di Torino</affiliation>
    </creator>
    <creator>
      <creatorName>Lange, Thomas</creatorName>
      <givenName>Thomas</givenName>
      <familyName>Lange</familyName>
      <nameIdentifier nameIdentifierScheme="ORCID" schemeURI="http://orcid.org/">0000-0002-5002-3679</nameIdentifier>
      <affiliation>iRoC Technologies</affiliation>
    </creator>
    <creator>
      <creatorName>Glorieux, Maximilien</creatorName>
      <givenName>Maximilien</givenName>
      <familyName>Glorieux</familyName>
      <nameIdentifier nameIdentifierScheme="ORCID" schemeURI="http://orcid.org/">0000-0002-6731-0455</nameIdentifier>
      <affiliation>iRoC Technologies</affiliation>
    </creator>
    <creator>
      <creatorName>Alexandrescu, Dan</creatorName>
      <givenName>Dan</givenName>
      <familyName>Alexandrescu</familyName>
      <nameIdentifier nameIdentifierScheme="ORCID" schemeURI="http://orcid.org/">0000-0002-8294-7534</nameIdentifier>
      <affiliation>iRoC Technologies</affiliation>
    </creator>
    <creator>
      <creatorName>Polo, Cesar Boatella</creatorName>
      <givenName>Cesar Boatella</givenName>
      <familyName>Polo</familyName>
      <affiliation>European Space Agency</affiliation>
    </creator>
    <creator>
      <creatorName>Codinachs, David Merodio</creatorName>
      <givenName>David Merodio</givenName>
      <familyName>Codinachs</familyName>
      <affiliation>European Space Agency</affiliation>
    </creator>
  </creators>
  <titles>
    <title>A Novel Error Rate Estimation Approach for UltraScale+ SRAM-based FPGAs</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2018</publicationYear>
  <dates>
    <date dateType="Issued">2018-11-22</date>
  </dates>
  <language>en</language>
  <resourceType resourceTypeGeneral="Text">Conference paper</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/3362341</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/AHS.2018.8541474</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode">Creative Commons Attribution Non Commercial No Derivatives 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;SRAM-based FPGA devices manufactured in FinFET technologies provide performances and characteristics suitable for avionics and aerospace applications. The estimation of error rate sensitivity to harsh environments is a major concern for enabling their usage on such application fields. In this paper, we propose a new estimation approach able to consider the radiation effects on the configuration memory and logic layer of FPGAs, providing a comprehensive Application Error Rate probability estimation. Experimental results provide a comparison between radiation test campaigns, which demonstrates the feasibility of the proposed solution.&lt;/p&gt;</description>
    <description descriptionType="Other">This work was supported as part of the RESCUE project that has received funding from the European Union's Horizon
2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No. 722325 and by the European Space Agency under contract No. 4000116569.</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/722325/">722325</awardNumber>
      <awardTitle>Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design</awardTitle>
    </fundingReference>
  </fundingReferences>
</resource>
38
64
views
downloads
Views 38
Downloads 64
Data volume 351.3 MB
Unique views 37
Unique downloads 57

Share

Cite as