Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms

We compare three platform-aware feedback control design flows that are tailored for a composable and predictable Time Division Multiplexing (TDM)-based execution platform. The platform allows for independent execution of multiple applications. Using the precise timing knowledge of the platform execution, we accurately characterise the execution of the control application (i.e., sensing, computing, and actuating operations) to design efficient feedback controllers with high control performance in terms of settling time. The design flows are derived for Single-Rate (SR) and Multi-Rate (MR) sampling schemes. We show the applicability of the design flows based on two design considerations and their trade-off: control performance and resource utilisation. The design flows are validated by means of MATLAB and Hardware-in-the-Loop (HIL) experiments for a motion control application.


INTRODUCTION
Feedback control applications are used in a wide range of applications developed for cost-sensitive industries that include industrial automation, consumer applications, automotive, avionics, and many others. A great number of these applications demand high performance, low cost, and a short time to market. Their control task is implemented by three sequential and repetitive operations: sense or measure data from the system under control (plant), compute the actuation signals, and apply the actuation signals to the plant such that its behaviour is regulated. In many real-life scenarios, the controllers are implemented onto embedded platforms with severe resource constraints (e.g., on computation and communication).
The current practice is to dedicate an embedded platform for each application to avoid sharing resources. This guarantees interference-free execution of applications, which is essential to achieve a high performance and reduce Time to Market (TTM). Without resource sharing, such design solutions often lead to expensive implementations due to high cost of hardware.
Bringing multiple applications within a single embedded platform is a potential solution for such expensive implementation, but it poses several challenges. The most notable among them is to deal with inter-application interferences. Common approaches to tackle this challenge include the use of multi-core embedded platforms, where each core of the platform is allocated to a single application. However, other shared resources, such as cache memories and interconnections, lead to interference between applications (Subramanian et al. 2015). An alternative approach is to partition (or virtualize) resources in both time (e.g., scheduling) and space (e.g., memory regions) such that all interference between applications due to resource sharing is avoided, and the development and integration of multiple applications in the platform is eased and sped up.
Implementing precise Time Division Multiplexing (TDM) policies onto the embedded platform execution is one technique to partition shared resources. One such example is the Composable and Predictable System on Chip (CompSOC) embedded platform (Goossens et al. 2017). This platform uses the Composable and Predictable Microkernel (CoMik), which cycle-accurately partitions the processor execution in fixed duration slots (Nelson et al. 2014). In each of these slots, an application executes without any interference from other applications. We consider TDM-based execution platforms, such as CompSOC, as the implementation platform for the feedback control applications.
Generally, the feedback control applications are required to guarantee stability and provide a required performance. However, complying with requirements and enhancing performance do not only depend on meeting timing deadlines, as is commonly regarded in real-time applications, but, as we will see, it also depends on richer timing characteristics that are derived from both the platform and the application executions.
Platform-aware model-based design of control systems has been reported to improve the control application performance (Morelli and Natale 2014). That is, the knowledge of the precise execution time information can explicitly be considered in the design of the controller to achieve a higher performance, as well as to meet the design constraints. In this work, we present feedback control design flows for efficient deployment of controllers onto composable and predictable platforms. As a study case, we exploited the CompSOC platform timing mechanisms to use equidistant and non-equidistant sampling intervals in the controller design.
Contributions: The contributions of this article are detailed as follows: • Single-rate (SR) design flow: Platform configured with equidistant sampling. This controller design has been adapted from Valencia et al. (2015) by replacing the pole-placement design with an Linear Quadratic Regulator (LQR) controller (Åström and Murray 2008). We use the settling time as the control performance metric. Thus, the LQR is tuned to optimise the performance. We use Particle Swarm Optimization (PSO) for the LQR tuning (Medina et al. 2017). We show that the SR design flow is suitable when the demand for the performance is relatively low (i.e., a longer settling time is acceptable). Better performance can be achieved with a higher resource utilisation. • Multi-rate Local Optimal (MRLO) design flow: Platform configured to obtain a finite sequence of periodic and non-equidistant sampling intervals. We further identify the most frequently occurring sampling interval (nominal sampling interval) in the sequence. We The remainder of the article is organised as follows. In Section 2, we present the related work from which we have taken many inspiring ideas. The composable and predictable TDM-based execution platform used in our work is presented in Section 3. The control application and the characterisation of its timing properties are described in Section 4. In Section 5, we describe the SR design flow, followed by the Multi-Rate (MR) design flows in Sections 6 and 7. In Section 8, we present the experimental study, where we give details about the motion control study case, the MATLAB and HIL experiments, the trade-off analysis between performance and resources allocated to the application, the impact of the platform settings reconfigurations on the performance, and the suggested design design guidelines. We finally draw conclusions in Section 9.

RELATED WORK
This work deals with the efficient implementation of feedback control applications on embedded platforms. For decades, the development of embedded control applications has been based on the separation of concerns principle between theoretical control and embedded systems disciplines (Årzén and Cervin 2005). The former is focused on control design with equidistant sampling intervals with hard execution deadlines. The latter is focused on developing scheduling mechanisms and computational models such that control applications meet these timing requirements during runtime. This design philosophy led to simpler control system models that often restrict control performance and stringent execution models with significant resource over-dimensioning. In contrast, a huge body of work has been reported on the platform-aware design philosophy where the emphasis is on co-design of control strategies and platform configurations (Cervin et al. 2003;Chang et al. 2017;Samii et al. 2009;Valencia et al. 2016;Wolf 2009). The idea is to take into account properties of platform resources in the control design and thereby improve the control performance.
The key considerations of computation-aware control design methods are the trade-off analysis between resource usage and control performance, efficient implementation and performance optimisation. A trade-off analysis between the number of processing units used for the control application and the performance is presented in Medina et al. (2017) for data intensive control loops. Integrated communication and computation (priority-based) scheduling for distributed control is solved by constraint logic programming formulation in Samii et al. (2009). The works in Aminifar et al. (2015) and Cervin et al. (2003) present analysis frameworks to analyse the effect of execution jitter on control performance. To this end, the sampling interval and delay play crucial role both in control performance and scheduling. They are often used as an interface between the control and embedded systems design paradigms. The optimal sampling interval is found with respect to the control performance in Cervin et al. (2011) and  and similarly, the delay is optimised in . Aminifar et al. (2016) present a response time analysis with self-and event-triggered execution of control applications. Similarly, Biondi et al. (2018) present response time analysis for controllers running under variable sampling intervals such as an engine control system.
Along the direction of communication-aware control design, there has been emphasis on control/schedule co-design considering industrial bus systems such as FlexRay Roy et al. 2016), CAN (Deng et al. 2016), as well as wireless networks (Bauer et al. 2014). The key consideration is optimisation and analysis of the control performance taking account the bandwidth restrictions, scheduling policy, and uncertainty of the communication systems in distributed implementations. Co-optimisation considering memory-mapping of control applications has been reported recently in Chang et al. (2017). In the context of electric vehicle, the power consumption by the controller becomes a crucial design parameter and hence, optimised for a longer battery life and control performance in Chang et al. (2014).
Overall, many state-of-the-art strategies offer synthesis frameworks to schedule and map applications onto a targeted embedded platform taking into account computation, communication, memory, and power resources. Our approach differs in a number of aspects and takes inspiration from many works (see Table 1). First, we deal primarily with feedback control applications implemented onto a composable and predictable platform that allows for resource sharing between applications (e.g., CompSOC platform (Goossens et al. 2017)). This platform uses a TDM scheduling protocol that virtualises the resources that are assigned to applications into time partitions where applications execute. This virtualisation enables independent development and execution of applications, simplifying the mapping and scheduling of the applications to time partitions per application (Çela et al. 2014), unlike works that must include the scheduling of applications in their designs (Aminifar et al. 2012;Arzen et al. 2000;Chang et al. 2018;Goswami et al. 2012;. The time-triggered behaviour of the virtualisation mechanism brings resource utilisation limitations for classical control approaches that are based on equidistant sampling intervals (Aminifar et al. 2012;Arzen et al. 2000;Åström and Wittenmark 1990;Cervin et al. 2003;Goswami et al. 2012;. In contrast, we exploit frequent execution of the control application within its assigned partitions to increase the sampling frequency and potentially the control performance, at the cost of dealing with non-equidistant sampling intervals, similar to works (Chang et al. 2018;van Zundert and Oomen 2018). We present different control laws (i.e., LQR, LMI-based), and we investigate their stability and optimisation (e.g., PSO-based LQR tuning). We show how the design flows can be used to integrate manual and automated procedures for each control strategy. We use MATLAB and HIL experiments to validate our design-flows (MathWorks 2018). As seen in Table 1, many works focus on timing analysis experimentation, whereas in our work we propose a HIL framework to verify the feasibility of implementing our control designs in a real platform. We draw the design guidelines that are based on the tradeoffs that we have explored on the resources assigned to the applications, their performance, and the impact of the platform settings to the aforementioned design constraints. In summary, our work is based on the TDM scheduling scheme that simplifies timing analysis of the applications, provides time-based performance metrics that allows to have real estimation of the effectiveness of our designs, allows for equidistant and non-equidistant sampling schemes to exploit performance, presents tradeoffs explorations to help the design flow selection, and presents HIL experiments to validate the implementation of our designs in a real embedded platform.

COMPOSABLE AND PREDICTABLE TDM-BASED EXECUTION PLATFORM
The CompSOC platform is configurable with processing units (processor tiles), interconnect Network on Chip (NoC), and memory units (memory tiles) (Goossens et al. 2017). An example architecture is shown in Figure 1. The processor tile is composed of a MicroBlaze soft-core processor, Fig. 1. Left: example of a TDM-based execution platform. Right: example for N = 4, with applications λ C and λ 2 (where λ C is the control application). The black blocks indicate the CoMik slots, while the blue and white blocks indicate the application slots for applications λ C and λ 2 , respectively. The TDM frame repeats infinitely. The numbers below the TDM frame denote the slots, which are indexed from 0 to 3.
instruction and data memory, and Direct Memory Access (DMA). The memory tile contains the Static Random-Access Memory (SRAM) memory interface, and the NoC provides the interconnections between the tiles. Resources are shared between applications with composable TDM arbiters, which means that the time slots allocated to each application are strictly periodic in time and of fixed duration with precision of a single clock cycle. This mechanism is used to partition the resources, such that the applications are loaded and run without affecting or being affected by other applications by even a single clock cycle. This makes it possible to implement a controller and emulate plant dynamics independently of other applications.
The CoMik micro-kernel partitions each processor execution in a TDM frame of size N slots, where each slot is composed of an application slot (i.e., where applications execute) of fixed duration ψ seconds and a CoMik slot (i.e., where the microkernel switches applications) of duration ω seconds. Thus, during runtime, each application is executed in its allocated slots and it is suspended every time a new CoMik slot starts. Its execution is only resumed in the next application slot assigned to it. This execution scheme is illustrated on the top-right side of Figure 1. Two applications λ C and λ 2 execute independently of each other within their allocated blue and white application slots, respectively.

EMBEDDED CONTROL SYSTEMS
Control applications regulate the dynamical behaviour of the plant. We deal with a common class of dynamical systems that are modelled as a CT Linear Time-Invariant (LTI) system, where x (t ) ∈ R n is the state of the plant, A c ∈ R n×n , B c ∈ R n×m , C c ∈ R n are the state, input, and output matrices, respectively. y(t ) ∈ R 1 is the output of the plant. u (t ) ∈ R m is the actuation signal (i.e., signal used by the actuators to be applied to the plant) that is computed by the control law.

Embedded Execution
A control task is the sequence of sensing (reading of sensors), computing (computation of actuation signals), and actuating (writing to actuators) operations. The execution of these operations defines the control task execution time and the sampling interval, which are essential control design parameters. • Control task execution time T : The control task does not execute instantaneously. Each of its operations has a finite execution time and the communication in the sensor-tocomputing, computing-to-actuating, and actuating-to-plant paths has also finite execution time. This results in an execution that begins with the sensing operation and terminates at the end of the actuating operation, and it is denoted by T . • Sampling interval S k : The sampling interval is defined as the time between two consecutive sensing operations at samples k and k + 1 and it is described by For the implementation, we make sure that the sampling interval is longer than the control task execution time T , i.e., S k > T .
These concepts are illustrated in Figure 2. In this work, we limit the scope to the delay resulting from the control task computation, since all the operations (i.e., sensing-computing-actuating) are performed within the embedded platform. Our methods can further be generalised to include the delay resulting from the communication between actuators-plant-sensors encountered in a distributed system.

Plant Discretisation
The plant dynamics, described in Equation (1), are sampled at DT instances t k with sample index k ∈ N ≥1 . Thus, the state of the plant can be described in DT as x k = x (t k ). Additionally, the actuation signal is updated under a Zero-Order Hold (ZOH) actuating scheme as u (t ) = u k for t ∈ [t k + T , t k+1 + T ). The DT system dynamics (with time delay) can be represented by Åström and Wittenmark (1990), We define the augmented system state obtaining the augmented higher-order system that can be written in a DT form, where I and 0 are the identity and zero matrices, respectively.

Control Performance
The objective of the feedback control application is to control the continuous-time system described in Equation (1) such that the output y(t ) → r as t → ∞, where r is the constant input reference signal. The time it takes for the system output y(t ) to reach and stay in a close region (≤2%) around the reference value r is the settling time.
In this work, the control performance is measured in terms of the settling time achieved by a controller, and we define the Quality of Control (QoC) as the inverse of the settling time as follows where a shorter settling time leads to a higher QoC. Note that the presented design flows are not restricted to any performance metric and they can be used considering other performance metrics. In Section 8.4, we will consider settling time (i.e., QoC = 1/settling time) and Integral Time-Weighted Absolute Error (ITAE) (i.e., QoC = 1/ t k |y k − r |) metrics. However, since settling time has direct implications on the real-time system behavior, we mainly focus on the results based on the settling time.

Resource Allocation and Utilisation
Consider a TDM frame of size N slots, where the total TDM frame duration is given by N (ψ + ω) seconds.
• Resource allocation: The periodic execution of the control application λ C requires evenly distributed allocated slots for an equidistant sampling. Considering the TDM frame of N slots, they can be numbered as {0, 1, 2, . . . , N − 1}. Thus, the resource allocation for λ C is given by a sequence A(λ C ) = (a 1 , a 2 , . . . , a M ), where a i ∈ {0, 1, 2, . . . , N − 1}. The number of slots allocated to λ C is denoted by M = |A(λ C )| with M ≤ N . M = 1 implies that only one slot is allocated to λ C and the allocation is periodic with period of N slots. For the cases with M > 1, to ensure even distribution of slots, the following conditions are imposed, 1 where Equation (8) is given to define the order of the slot allocation, such that each slot allocation a i is followed by a slot allocated in the future a i+1 , and not otherwise. Equation (9) conditions the slots allocation to have a period Also, the expression a 1 + N − a M considers the period from the last allocated slot a M and the first allocated slot a 1 of the following TDM frame. Finally, the condition in Equation (10) is given to guarantee that N is a multiple integer of the separation between two consecutive allocated slots within the TDM frame and therefore to achieve periodic allocation. • Resource utilisation: Utilisation is referred as the resource the control task of a control application λ C uses as a fraction of the total TDM frame. This is given by where E is the number of executions of the control task within ψ . E = 1 for SR sampling (detailed in Section 5.1) and E = ψ T for MR sampling (detailed in Sections 5.1 and 6.1). Note that λ C execution is not interrupted within ψ . λ C is designed such that within ψ the control task runs once or multiple times with execution time T .
In Figure 3, we show examples of resource allocation and utilisation for N = 4. Within the white slots any application may run (e.g., multimedia application), but we focus on the blue slots where λ C executes. In the top of the figure, we present examples of evenly distributed slots. Whereas at the bottom of the figure, we present an example of unevenly distributed slots. We detail these examples (labeled from (a) to (e)) as follows: • In (a), when all the slots are used A(λ C ) = {0, 1, 2, 3}, M = 4, and the control task runs twice within ψ , the resource utilisation U (λ C ) = 4 2T ψ +ω 100%. • In (b) and (c), for allocations A(λ C ) = {0, 2} and A(λ C ) = {1, 3}, M = 2, and when the control task runs three times within ψ , the resource utilisation U (λ C ) = 2 3T ψ +ω 100%. • Alternatively, in (d) a single slot can be allocated to λ C with M = 1, and when the control task runs only once within ψ , U (λ C ) = T ψ +ω 100%. • In (e), we present an example of unevenly distributed slots allocated to λ C , where A(λ C ) = {0, 1}, M = 2, and the control task runs twice within ψ . From Equations (8)-(10), note that the first and third conditions are met, meaning that the number of slots are correct. However, the second condition is violated with a 2 − a 1 a 1 + N − a 2 , and the periodicity is violated by not allocating evenly distributed slots.

Platform-awareness and Its Constraints
We consider the TDM-based execution scheme in the CompSOC platform illustrated in Figure 1, and the control task execution described in Section 4.1 and illustrated in Figure 2. These executions give us the precise timing information that can be used in the design of the controller. This is what we refer to as platform-awareness and to compare the SR and MR design flows presented in this article, we have constrained the platform-awareness with the following conditions: • The number of slots allocated to λ C is constrained by the conditions in Equations (8)-(10). Such an allocation allows us to directly compare the three design flows, because it allows both SR and MR sampling. It is important to notice that the allocation of slots for MR controllers is not limited to evenly distributed slots but also contiguous and unevenly distributed allocation of slots can be used, as presented in Valencia et al. (2016), where contiguous allocation led to a higher QoC. • The control task of λ C always starts running at the beginning of the allocated application slots and its operations (i.e., sensing, computing, actuating) execution do not spread across multiple slots. • Given λ C , its control task runs E = 1 time for the SR design flow and E = ψ T times for the MR design flows within each of its allocated application slots. To that end, we configure ψ ≥ ψ T T .

SINGLE-RATE DESIGN FLOW
In this section, we present the platform-aware design flow for feedback controllers whose execution is based on a SR sampling scheme.

Single Rate Sampling
A SR sampling (equidistant sampling interval) scheme for λ C is achieved by customising the platform such that it meets the constraints defined in Section 4.5. Recall that for this type of sampling the control task runs only once within ψ . Thus, the single rate sampling interval for λ C with allocation A(λ C ), and a TDM frame with N , M, ψ , and ω is given by Let us consider an example where the TDM frame is composed of N = 4 slots, and allocation with M = 2 slots to λ C (depicted in Figure 4). The SR sampling interval is h SR = 2(ψ + ω) seconds. At kth sample, the sampling interval is given by S k = h SR .

Control Design
The design of the SR controller can be done with a classical model-based control methodology (Kuo 1992), e.g., pole-placement or LQR.
Control law: The control law in this design design flow is updated with a sampling interval h SR and it is of the form where K and F are the feedback and feedforward controllers, z k is defined as per Equation (4), and r is the constant input reference signal. Closed-loop system dynamics: Given the control law in Equation (13), the closed-loop system dynamics are obtained by using the DT augmented higher-order system from Equation (5) as Feedback control gain K: The feedback gain K is designed using the LQR methodology that minimises the DT cost function Platform-Aware Control Design Flows for TDM-based Execution Platforms 32:11  withQ 0 andR 0, the DT state and control weighting matrices of the LQR 2 . Having largeQ compared toR puts emphasis on making the state small possibly at the cost of large actuation signals but potentially leading to a short settling time. By increasingR, large actuation signals are penalised, typically leading to a slower response. To minimise the settling time and maximise the QoC as per Equation (7) an LQR tuning is used to find the values ofQ andR. In this work, the PSO algorithm of Medina et al. (2017) has been used. This algorithm explores the tuning of theQ andR matrices as a parallel problem. It defines a swarm population composed of a finite number of individuals (i.e., random values that set the contents of theQ andR matrices). Each individual moves according to a velocity that is determined in every iteration by a random component, a personal best position of each individual, and a global best position of the swarm. Thus, in each iteration the feedback control gain K is designed and the QoC of the controller is evaluated. Feedforward control gain F : The feedforward gain F is computed, for the closed-loop dynamic described in Equation (14), by following the design in Hellerstein et al. (2004).

Design Flow
We propose the design flow shown in Figure 5, 3 which is composed of seven parts. (i) λ C requirement on QoC and T shape the resource utilisation U (λ C ). (ii) The platform settings (Section 3) and the resource allocation (Section 4.5) can be derived from the targeted resource utilisation. (iii) From there, the SR sampling interval is computed (Section 5.1). (iv) The feedback control gain K is computed by using the PSO (Section 5.2). (v) The static feedforward control gain F is computed. (vi) The requirement on QoC is evaluated and if it is met, the design flow ends. (vii) If the QoC requirement is not met, then the feasibility of varying the resource utilisation U (λ C ) is verified. If the resource utilisation can be modified, then one can either reallocate more slots to the application (i.e., increasing M as long it is M < (N − # of other applications running in the platform)) or change platform settings (i.e., ψ , ω, N ), to derive new timings for the execution of λ C (e.g., sampling interval h SR ). Otherwise, if the resource utilisation cannot be modified, then no feasible solution can be found with this design flow on this platform.

MULTI-RATE LOCAL OPTIMAL DESIGN FLOW
In this section, we present the platform-aware design flow for feedback controllers whose execution is based on a MR sampling scheme and their performance is optimised for their nominal sampling interval.

MR Sampling
A MR sampling (finite and periodic sequence of non-equidistant sampling intervals) scheme for λ C is achieved by customising the platform such that it meets the constraints defined in Section 4.5. Recall that for this type of sampling the control task runs where the variation of T is very small (i.e., due to the interference-free characteristics of the Comp-SOC platform) and is equal to the summation of the last h MR 1 sampling interval within ψ , the remaining time within ψ that is given by ψ − ψ h M R 1 h MR 1 , and the time between two consecutive allocated application slots that is given by ( N M − 1)ψ + N M ω. In Figure 6, we illustrate the MR sampling with an example where N = 4, M = 2, and A(λ C ) = {0, 2}. Within each ψ , the control task runs is the nominal sampling interval, since it occurs more frequently, whereas is h MR 2 is the longer and less frequently occurring sampling interval. At the kth sample, the sampling interval is given by

Control Design
The design of the MRLO controller exploits the frequent runs of the control task within ψ to achieve a high performance. Essentially, we optimise the performance of an independent controller designed for the nominal sampling interval h MR 1 using the SR design flow detailed in Section 5. To guarantee that the system is stable during runtime, when the system runs between the periodically non-equidistant sampling intervals, we use a Lyapunov-based design that includes the controller designed for h MR 1 to obtain the controller for the sampling interval h MR 2 .
. For MRGO Section 7.1: The periodic sequence of non-equidistant sampling intervals is given by H

Control law:
The control law changes with the sampling intervals h MR 1 and h MR 2 , and it is given by

Closed-loop system dynamics:
The closed-loop dynamics depend on the sampling intervals and the control law. It is obtained using the DT augmented higher-order system dynamics in Equation (5). With sampling interval h MR j and the control law in Equation (18), the closed-loop dynamics is given by whereÂ j andB j are the DT augmented system matrices for the sampling interval h MR j . Switching behaviour: The sampling intervals switch between h MR 1 and h MR 2 . Thus, the closedloop dynamics switch between the two systems (Â 1 +B 1 K 1 )z k +B 1 F 1 r and (Â 2 +B 2 K 2 )z k +B 2 F 2 r according to the order of the periodic sequence of non-equidistant sampling intervals. Stability of this switched system is governed by the feedback gains K 1 and K 2 . Note that the feedforward gains do not influence the stability of the overall system. Therefore, for the stability analysis, we consider the system matrices, α 1 =Â 1 +B 1 K 1 and α 2 =Â 2 +B 2 K 2 . For the example in Figure 6, the switching sequence is given by α 1 → α 1 → α 2 · · · .
Nominal sampling interval: The focus of this controller design flow is to optimise the controller QoC by locally optimising the performance of the control gain that is designed for the nominal sampling interval. It is important to configure ψ ≥ ψ T T , such that the control task runs multiple times within ψ as depicted with the example in Figure 6, where ψ ≥ 3T leading to a nominal sampling interval h MR 1 that is repeated ψ T − 1 = 2 times within ψ . Nominal feedback control gain K 1 : The nominal feedback control gain K 1 is computed for the nominal sampling interval h MR 1 , following the methodology described in Section 5.2. Switching feedback control gain K 2 : To guarantee the stability of the overall system under the switching behaviour explained above, we perform the DT Lyapunov stability test to find a Common Quadratic Lyapunov Function (CQLF) P ∈ R n×n , such that the LMIs P 0, α 1 Pα 1 − P ≺ 0, and α 2 Pα 2 − P ≺ 0 are feasible. With these LMIs, we evaluate the stability of the system as well as compute the switching feedback control gain K 2 using the following procedure. First, by using α 1 and α 2 on the LMIs, we solve for K 2 . However, this leads to non-linear matrix inequalities (i.e., leads to a term where K 2 is multiplied by P). To solve this, we rewrite the LMIs by using the Schur complement (Crabtree and Haynsworth 1969) as follows: To resolve the above non-linearity, we use a variable substitution by defining Y = P −1 , where Y ∈ R n×n , and we pre-and post-multiply by the linearisation operator diag(Y , I) to obtain 4 Finally, we define where W ∈ R n . Thus, the LMIs are reformulated as and if there exist matrices Y and W , the system is stable with the switching between the systems α 1 , and α 2 , and K 2 is given by Equation (22). Feedforward control gains F 1 and F 2 : The feedforward gains F 1 and F 2 are computed for the closed-loop dynamics α 1 and α 2 following the design in Hellerstein et al. (2004).

Design Flow
We propose the design flow shown in Figure 7, which is composed of ten parts. (i) λ C requirement on QoC and T shape the resource utilisation U (λ C ). (ii) The platform settings (Section 3) and the resource allocation (Section 4.5) can be derived from the targeted resource utilisation. (iii) From there, the MR sampling intervals are computed (Section 6.1). (iv) If it is feasible to design the feedback control gain K 1 , then the design flow continues to part (v) or it goes to part (ii) otherwise (i.e., a different resource utilisation is selected to vary the nominal sampling interval). (v) The feedback control gain K 1 is computed by using the PSO (Section 5.2). (vi) Later, we evaluate the feasibility of the LMIs to guarantee stability using K 1 as per Equation (23). If the solution is infeasible, then it is necessary to modify the resource utilisation. That is, reallocate resources or change platform settings to derive new timings for λ C . (vii) If the solution is feasible, then the feedback control gain K 2 is computed as per Equation (22). (viii) The static feedforward control gains F 1 and F 2 , are computed. (ix) The requirement on QoC is evaluated and if it is met, the design flow ends. (x) If the QoC requirement is not met, then the feasibility of varying the resource utilisation U (λ C ) is verified. If the resource utilisation can be modified, then one can either reallocate more slots to the application (i.e., increasing M as long it is M < (N − # of other applications running in the platform)) or change platform settings (i.e., ψ , ω, N ), to derive new timings for the execution of λ C (e.g., sampling interval h MR 1 and h MR 2 ). Otherwise, if the resource utilisation cannot bet modified, no solution can be found with this design flow on this platform.
Unlike the SR design flow in Section 5.3, the control gains K 1 and K 2 cannot be freely designed. Since K 1 is optimised for performance, this might be an aggressive control gain that might lead to an infeasible solution to compute K 2 .

MULTI-RATE GLOBAL OPTIMAL DESIGN FLOW
In this section, we present the platform-aware design flow for feedback controllers whose execution is based on MR sampling. Their design offers a stabilising solution that transforms the switching MR system to a classic LQR control design problem, where heuristics are used to find the tuning parameters of the LQR to achieve high QoC.

MR Sampling
A MR sampling (finite and periodic sequence of non-equidistant sampling intervals) scheme for λ C is achieved by customising the platform such that it meets the constraints defined in Section 4.5. Recall that for this type of sampling the control task runs ψ T times within ψ , with finite and periodic sequence of sampling intervals h MR j where j ∈ {1, 2}. This sequence is represented by the tuple  (16) and (17) from Section 6.1.

Control Design
The MRGO controller is designed to find a solution for the overall MR switched system to achieve high performance. Our technique transforms the overall MR control design problem to the classical LQR design by using a time-lifted reformulation.
Control law: The control law is given by where K i and F i are feedback and feedforward gains used when the sampling interval S k = H (i).
Thus, there are ρ combinations of (K i , F i ). This is illustrated in Figure 6, where ρ = 6 combinations of these control gains are used sequentially and according to the order of sampling intervals in the tuple H . Closed-loop system dynamics: Closed-loop system considering the DT augmented higherorder system dynamics in Equation (5) and control law in Equation (25) is given by whereÂ i =Â andB i =B are the augmented state and input matrices for the sampling interval S k = H (i). Switching behaviour: Since the sampling intervals periodically repeat according to the order in H , the resulting DT system dynamics periodically switch between ρ closed-loop dynamics given by Equation (26).
Control problem: Let us first define the DT representation of the cost by where Q c and R c are the CT state and control weighting matrices, respectively. The DT state and control weighting matrices are represented byQ i andR i , respectively (Valencia et al. 2016). The control problem can now be formulated as follows: Given (J ), subject to system in Equation (5), where this problem does not have a closed-form solution for arbitrary t k . However, on the Comp-SOC platform, the sampling intervals occur in the periodic sequence H . Hence, the set of possiblê A i andB i can be pre-computed and result in a DT Linear Periodically Time-Varying (LPTV) system for which the control problem can be solved using periodic Riccati equations. Time-lifted Reformulation: For a DT-LPTV system with ρ sampling intervals, the dynamics and cost have the periodicity propertŷ With a TDM period index δ , the time-lifted reformulation (Bittanti and Colaneri 2008) gives the dynamics over one TDM period, where 5 Platform-Aware Control Design Flows for TDM-based Execution Platforms 32:17 and the cost can be written as Q =Ā QĀ ,R =R +B QB , using the augmented variables and using the dynamics within the TDM period Feedback control gains K i : Note that the matrices (Ã,B,Q,R) in Equations (28) and (29) do not depend on the TDM period index δ , i.e., they are time-invariant. The lifted problem thus has the standard time-invariant DT LQR form, which can be solved efficiently. For this lifted reformulation standard optimal control methods can find the optimal solution (Åström 1970;Bertsekas 2005), whereP is the unique positive definite solution to the Discrete-Time Algebraic Riccati Equation Furthermore, V (z) = z P z is a Lyapunov function that ensures stability for the optimal control actionsū This is the solution to the lifted problem over one TDM period, and can be transformed into a state feedback for the original DT-Linear Time Variant (LTV) system described with Equation (25). From P ρ+1 =P, the solutions P i can be found from the solution to the standard finite horizon Discrete-Time Dynamic Riccati Equation (DDRE), which represents the Discrete-Time Periodic Riccati Equation (DPRE) when P i+ρ = P i (Varga 2008). The feedback control gains K i are computed by Feedforward control gains F i : The feedforward gains are computed for the closed-loop dynamic α (k,i ) following the design in Hellerstein et al. (2004).
Q c and R c matrices initialisation: In this design flow, we have shown that the CT cost function is translated into its DT equivalent. This cost function is further extended for the time-lifted reformulation of the DT-LPTV representation of the system that switches between the sampling intervals in H . This means that we need to initialise the CT Q c and R c matrices or the DTQ i and R i matrices, and evaluate their impact on the QoC. To initialise the values of the Q c and R c matrices, we use a heuristic that consists of choosing the diagonal values of these matrices, such that the control performance is optimised in DT. To improve the design flow it would be necessary to automate the optimisation of theQ i andR i matrices for higher QoC. However, this procedure it not investigated in this work.

Design Flow
We propose the design flow shown in Figure 8, which is composed of seven parts. (i) λ C requirement on QoC and T shape the resource utilisation U (λ C ). (ii) The platform settings (Section 3) and the resource allocation (Section 4.5) can be derived from the targeted resource utilisation. (iii) From there, the periodic sequence H of non-equidistant sampling intervals is computed (Section 7.1). (iv) Thus, the feedback control gains K i are computed as per Equation (34) following the design in Section 6.2. (v) The static feedforward control gains F i are computed. (vi) The requirement on QoC is evaluated and if it is met, the design flow ends. (vii) If the QoC requirement is not met, then the feasibility of varying the resource utilisation U (λ C ) is verified. If the resource utilisation can be modified, then one can either reallocate more slots to the application (i.e., increasing M as long it is M < (N − # of other applications running in the platform)) or change platform settings (i.e., ψ , ω, N ), to derive new timings for the execution of λ C (e.g., sampling intervals h MR 1 and h MR 2 ). Otherwise, if the resource utilisation cannot bet modified, then no solution can be found with this design flow on the platform.
Unlike the SR and MRLO design flows in Sections 5.3 and 7.3, none of the control gains K i can be freely designed. In this particular design flow, the design of the K i gains are subjected to the cost function in Equation (29).

EXPERIMENTAL STUDY
In this section, we present the experimental study we have carried out to evaluate the design flows presented in Sections 5 to 7. We will dive into details of the plant that we used, the MATLAB and HIL experimets, the trade-off analysis derived from two design considerations: QoC and U (λ C ). Moreover, we will evaluate the impact of the platform settings on QoC, and finally we present design guidelines.

Platform Configuration
The allocation of slots to applications, N , ψ , and ω, are defined at design time. ω is fixed at 40.96μs, whereas ψ is application dependent and we have set it up with values in the range of 3-30ms for the experiments reported in this article. The control task execution time is measured during runtime and it is T = 0.99ms.
The customisation of the platform settings has a strong influence on the control task execution time. On the one hand, choosing ψ = T only allows for the SR design flow implementation, because the control task will execute once within ψ . This implies that if T is short, ψ will be also short. Thus, ψ → ω, and therefore the resource utilisation U (λ C ) goes down significantly, because more resources will be used by the CoMik microkernel. On the other hand, choosing ψ T allows for both SR and MR design flows implementation. If the SR design flow is used in this scenario, then the resource utilsiation will decrease, because the control task will run once within ψ and the remaining available processing time within ψ will be unused. In essence, the SR design flow has a lower resource utilisation and this is where it falls short. To avoid this lower resource utilisation, we have used MR design flows. They use longer ψ (i.e., to avoid ψ → ω) and ψ is used as much as possible (i.e., ψ T times).

Setup: Motion Control System
We consider a motion control system that is composed of a mechanical setup, an electrical circuit for actuation, and an embedded platform. The mechanical setup is composed of two masses connected to each other by a flexible bar. The motor is connected directly to one of the masses, and two encoders measure the rotation in each mass (Geelen et al. 2016). The electrical circuit converts the digital actuation signal to an analog input that is applied to the plant. An instance of the CompSOC platform (depicted in Figure 1) where λ C executes, is synthesised on a Xilinx ML605 Virtex6 FPGA-based development kit (Xilinx 2018).
The mechanical and electrical circuits are described with the CT LTI model from Equation (1), where the state of the plant x (t ) = [ θ 1 θ 2 ω 1 ω 2 ] is composed of angular positions (θ 1 , θ 2 ), angular velocities (ω 1 , ω 2 ), and the state and input matrices are defined by (adapted from the model presented in Geelen et al. (2016))

MATLAB Experiments.
The MATLAB simulation is essential to verify the correct functionality of the control gains that have been designed for the previously described design flows. This experiment consists of the following steps. (i) Control design of the feedback and feedforward gains for the respective design flow (i.e., SR, MRLO, or MRGO). (ii) Simulation of the DT system by

HIL Experiments.
The HIL experiment allows for the validation of the control design flows. These are validated by implementing the controller and emulating the plant dynamics on independent processor tiles. Hence, there is an exchange of electrical signals between the controller and the plant (Karpenko and Sepehri 2006;Ogan 2015;Palladino et al. 2009;Truong 2012). We built a HIL experiment using one instance of the CompSOC platform with the architecture shown in Figure 1. One processor tile runs the control application under a TDM-based execution scheme. The other processor tile runs the DT plant dynamics at a high frequency ( T ) to emulate the CT behaviour of the plant.
The HIL experiment can be divided in two parts. (i) Control application implementation, where we simulate the sensing and actuating operations as read and write operations of the system states and actuation signals to and from off-chip memory locations. In between these operations the computation of actuation signals (u k , Equation (13); u 1,2 , Equation (18); and u i , Equation (25)) is done by using the control gains calculated off-line by the design flows described in Sections 5-7, respectively. (ii) The emulation of the CT plant dynamics is done by running the DT plant dynamics of the plant at a very high frequency, with the DT dynamics (without time delay (Åström and Wittenmark 1990)) of the plant represented by x k+1 = σx k + ηu k , where η = Γ 1 (τ ) and the state of the plant is sampled at S k = 100μs. Figure 9, we compare the MATLAB and HIL experiments, with y MATLAB and y HIL the outputs, respectively. In these experiments, the platform has been configured with ψ = 5.95904ms, N = 10 slots, and M = 1 slot. The design flows compute the following timing properties: h SR = 60ms, h MR 1 = 1ms, and h MR 2 = 56ms. In Figure 9(a) the comparisons of the simulation outputs is presented. In essence, the three design flows have been simulated and it can be seen the difference between SR (top plot) and MR (middle and bottom plots) sampling (i.e., equidistant and non-equidistant samples). Note that both MATLAB and HIL experiments show very similar results, which means that the implementation of such controller is feasible for the Platform-Aware Control Design Flows for TDM-based Execution Platforms 32:21 Fig. 10. Comparison of the QoC with respect to the resource utilisation U (λ C ) for each design flow.

MATLAB-HIL Comparison. In
studied motion system. In Figure 9(b) the absolute errors of the simulation outputs are shown. The error for the SR design flow (top plot) is very small due to the use of a single controller. Finally, the error for the MR design flows (middle and bottom plots) appears with the switching between h MR 1 and h MR 2 but it does not exceed 4% with respect to the static reference signal that is set to 0.05 radians (see Figure 9(a)). These results show that both type of experiments are closely matching. In what follows, we focus on analysing the results and perform trade-off analysis.

Trade-off Analysis: QoC and U (λ C )
We run several experiments to evaluate the impact of U (λ C ) on the QoC for each design flow. To that end, we set the platform up with ω = 40.96μs. We varied ψ = 2.95904, 4.95904, 5.95904ms, N = 1, 2, 6, 10 slots, and M = 1 slot or M = 10 slots with N = 10. In Figure 10, we compare the QoC based on settling time (see Figure 10(a)) and ITAE (see Figure 10(b)) with U (λ C ). As expected, it can be seen that the trends depend on the selected metric. We explain further results using the QoC based on the settling time (see Equation (7)). It can be seen, a common trend is the increase in QoC when more resources are assigned to λ C . One can also note that the MRLO and MRGO design flows bring high performance with at least ≈ 40% of the resources allocated to λ C . Another interesting result is that the QoC of the SR design flow only reaches up to 25% of the resource utilisation. This is due to the fact that ψ T . Thus, even when the TDM frame only has one application slot N = 1, a great part of ψ is unused. This lower platform resource utilisation is one of the shortcomings of the SR design flow.

Impact of Platform Settings
As presented in the design flows, the platform settings can be reconfigured to meet design requirements. However, the CoMik slot duration ω can be considered to be limited by the implementation (i.e., we run the hardware as fast as possible and minimise ω). Thus, we focus on the application slot duration ψ and the number of slots within the TDM frame N . We varied these settings for a control task execution time T = 0.99ms. In what follows, we only refer to Figure 11 for ease of reading. Please refer to Table 2 to see the corresponding sampling intervals used in the presented experiments in Figure 11.
• Application slot duration ψ: In Figure 11(a), we present the results of the QoC in terms of ψ values. The increase in ψ , leads to a QoC deterioration of the SR design flow, since  Top: Sampling intervals when ψ is varied (Figure 11(a)). Bottom: Sampling intervals when N is varied (Figure 11(b)).
the sampling interval h SR increases. Similar results can be seen for the MRGO design flow when M = 1. The QoC in this case decreases with longer ψ , due to the enlargement of the sampling interval h MR 2 (29, 47, and 56ms for an increasing ψ ) while h MR 1 does not change. When M = 10, h MR 2 remains constant at 2ms regardless of ψ . This leads to a fairly high and constant QoC, since the sampling interval h 2 MR does not change significantly. The MRLO design flow QoC shows a different trend for which a longer ψ improves the QoC. This is due to the fact that the control task runs more often within ψ (2, 4, and 5 for an increasing ψ ). For the same design flow, the impact of increasing M to 10 slots is reflected by an overall increase in the QoC due to shorter sampling intervals h MR

Design flow
Choice of ψ Choice of N

SR
Small ψ is always good -Depends on application sharing -Small is better

MRLO
Large ψ is always good -Depends on application sharing -Small is better

MRGO
-Less sensitive to ψ -Small is recommended -Depends on application sharing -Small is better • TDM frame slots number N : In Figure 11(b), we present the results of the QoC in terms of the frame slots nummber N , for a fixed M = 1, while varying N with 1, 2, 5, and 10 slots, and varying ψ with 2.95904 and 5.95904ms. For the SR design flow, increasing N enlarges the sampling interval h SR that leads to a QoC deterioration. For the MRLO design flow, we see two scenarios for ψ = 2.95904 and 4.95904ms. For the smaller ψ , we notice that the QoC decreases with larger values of N . This enlarges the TDM frame with more slots and make the sampling interval h MR 2 longer (2, 5, 17, and 29ms for an increasing N ), which negatively influences the QoC. For the larger ψ , the controller manage to achieve the reference with a high QoC regardless of N . This happens because the control task runs more frequently withinψ , meaning that the controller can sample and control more frequently (with nominal sampling interval and feedback control gain h MR 1 and K 1 , respectively). For MRGO design flow, the QoC presents two type of behaviours. The former one is given by a high QoC for N = 1, 2 slots. This results from the short sampling intervals in those configurations. The latter one is given by a decreasing QoC for N = 6, 10 slots, which is due to the increasing sampling interval h MR 2 .

Design Guidelines
One can notice that there is no optimal design flow that guarantees fastest settling time and least amount of resources. However, we see that each design flow has its benefits and drawbacks depending on the requirements and platform configurations. Therefore, we present the following design guidelines that are illustrated in Figure 12 accompanied with Table 3.
• QoC and resource utilisation U (λ C ): When resource utilisastion is low (below 25%, which further depends on the platform configuration), SR and MRGO perform better than MRLO. When U (λ C ) is in the range of 25-70%, both MRGO and MRLO can be used while MRGO performs better. When U (λ C ) is in the range of 70-80%, both MRGO and MRLO can be used while MRLO performs better. When U (λ C ) > 80%, both MRGO and MRLO perform equally good. • Choice of ψ: For the SR design flow, a smallerψ is always good. A larger ψ is recommended for MRLO for a high U (λ C ). MRGO is less sensitive to the choice ψ while a smaller ψ is recommended. • Choice of N : A smaller N is good for all the three design flows. However, a small N implies less number of applications can be executed on the platform. Depending on the number of other application that need to run on the platform, N should be chosen as small as possible.

CONCLUSIONS
We have presented three platform-aware control design flows that have been validated and compared using MATLAB and HIL experiments. We have shown in our experiments that each design flow can be used depending on the requirements that are given on the QoC and a targeted resource utilisation. Furthermore, we have shown how the time precision offered by composable and predictable platforms can be exploited to design SR and MR control systems considering various design constraints. For future work, a multi-rate observer/estimator module will be designed to address the cases where all states are not measurable. This is often the case in real-life physical systems.