Conference paper Open Access
Zou; Gottardi; Perenzoni; Perenzoni; Stoppa
This paper reports on a QVGA vision sensor embedding 160 column-level digital processors executing real-time tunable scene background subtraction for robust event detection. The single-ramp column-parallel ADCs are used to estimate the pixel variations and detecting anomalous behaviors against two reference images stored in on-chip. The sensor generates a 160x120 pixel bitmap associated to potential alert conditions. The chip is powered at 3.3V/1.2V for the analog/digital parts and consumes 1.6mW when operating at 15fps dispatching gray-scale image and a quarter QVGA bitmap.