Delay-based Design of Feedforward Tracking Control for Predictable Embedded Platforms

This paper presents a design technique for feedforward tracking control targeting predictable embedded platforms. An embedded control implementation experiences sensor-to-actuator delay which in turn changes the location of the system zeros. In this work, we show that such delay changes the number of unstable zeros which influences the tracking performance. We propose a zero loci analysis with respect to the delay and identify delay regions which potentially improve tracking performance. We utilize the analysis results to improve tracking performance of implementations targeting modern predictable embedded architectures where the delay can be precisely regulated. We validate our results by simulation and hardware-in-the-loop (HIL) implementation considering a real-life motion system.


I. INTRODUCTION
High precision motion control systems play an important role in many domains like robotics [1], lithography [2], and many more [3]. They perform fast and accurate tracking of a predefined reference signal [1], e.g., motion path. Feedforward tracking controllers are commonly used to achieve this high precision [4]. In such control structures, a feedback component ensures the stability of the closed loop system, and the feedforward component enables the reference tracking [5].
The current trend in many domains is to use embedded platforms to realize a cost and energy effective control implementation [6]. Such platforms usually run dedicated applications and are a part of a larger mechanical or electrical system [7]. They usually have limited computation resources and deal with critical timing constraints [8]. It is important to analyze these constraints and their implication on applications. In the context of control applications, the most important artifacts are sensor-to-actuator delay and sampling period [9]. In the commercial-of-the-shelf (COTS) platforms, an embedded implementation often experiences timing-varying nature of execution which implies timevarying delay and sampling period [10].
For the control perspective, a possible solution to deal with the above time-variation is designing a robust controller. These approaches are either H ∞ based [11] or LMI (linear matrix inequality) based [12] in which a controller is designed to stabilize the system for a given range of sampling periods and delays. Such robustness comes at the cost of degraded performance which is often not acceptable in high precision motion applications. In this paper, we propose 1  {s.m.haghi, d.goswami, k.g.w.goossens}@tue.nl, fwgsbc@live.com an alternative approach where we consider a predictable implementation platform with limited/no time-variation in execution time. Such platforms offer extensive timer mechanism to extract the precise knowledge of delay and sampling period at the design time which can be exploited in the controller design for an improved performance [13].
One of the timing constraints of embedded platforms is sensor-to-actuator delay. It is a common conclusion in the literature that a higher amount of delay negatively influences the control performance [14], [15]. Consequently, the practice is to reduce the delay for a better performance at a higher hardware cost (e.g., higher priorities in the scheduling or a higher processing resource usage [16]). On the contrary, we observe that a higher delay may potentially improve the control performance. We show that the sensor-to-actuator delay influences the systems dynamics and changes the location of system zeros. In particular, we show that the sensor-toactuator delay may change the number of unstable zeros (zeros which are outside the unit circle in Z-plane) which in turn influences the feedforward tracking performance. The performance of model-inversion based feedforward controllers is highly dependent on the number of unstable zeros of the system [5]. There are different approaches to design feedforward controllers that try to deal with unstable zeros in different teachniques, e.g., NPZ-Ignore [17], ZPETC [18] and ZMETC [19]. Regardless of the approach, a change in the number of unstable zeros impacts the feedforward performance significantly. A higher number of unstable zeros degrades the performance. Therefore, if an increase in the delay decreases the number of unstable zeros, it improves the performance of feedforward control. In view of this observation, we treat sensor-to-actuator delay as a design parameter in the controller design to find an optimal delay value with the lowest possible number of unstable zeros. Our contributions: Our main contributions are the following: • We characterize the impact of sensor-to-actuator delay on the number of unstable zeros (and hence, the system performance). We show that the sensor-to-actuator delay can be used as a design parameter in the feedforward tracking control. • Based on the above characterization, we propose a design method for feedforward tracking controllers targeting predictable embedded platforms for an improved performance. • We validate our design method considering a predictable embedded platform with an hardware-in-the-loop (HIL) implementation. This section illustrates impact of the sensor-to-actuator delay on control systems implemented on a embedded platform. We use a motivating case study for illustration.

A. Sensor-to-actuator delay
Let us consider a controllable linear time-invariant (LTI) continuous system. The state-space of the system is given by,Ẋ where X(t) ∈ R n are the states of the system, U (t) is the input, Y (t) is the output of the system. A control loop is implemented by sequentially and periodically performing three main operations -sensing, computation and actuation.
In the sensing operation, the states of the system are read by the sensor at the time instances t k which are defined as: In the computation operation, the controller calculates the next control value u[k]. In the actuation operation, the actuator updates the control value u[k] of the system. The time between two sensing operations is called sampling period h. As illustrated in Fig. 1, execution of the three operations requires finite time on an embedded platform. We denote execution times of the sensing, computation and actuation operations by T s , T c and T a respectively. T o is the summation of communication overheads of sensor-to-controller and controller-to-actuator. The time from the start of the sensing operation to the end of the actuation operation is called sensor-to-actuator delay D c which is given by, We focus on the case where delay D c is shorter than sampling period h,

B. Delay modeling
Considering h and D c , the discrete-time equivalent of system (1) is [14], where φ = e Ah , and e As Bds, To rewrite the equations in the standard state-space representation, we augment the state with the delayed actuation by defining ξ T . With this new augmented states we have [20], where From the definition of Γ 0 and Γ 1 it is easy to note that both φ aug and Γ aug are dependent on D c .

C. Zeros of delayed system
We find the system zero polynomial by transforming the state space model to transfer function representation [21]. The transfer function of the discrete-time augmented statespace (6) is given by, where G(z) is the transfer function, ∆(z) is the zero polynomial and P (z) is the characteristic (or pole) polynomial. From the definition of matrix inverse we have: where adj(.) is the adjugate of the matrix and det(.) is its determinant. det(.) is the characteristic polynomial P (z). Therefore from (7), the zero polynomial is System discrete-time zeros are the roots of ∆(z) = 0. Since φ aug and Γ aug are functions of D c , we compute discretetime system zeros by solving ∆(z) = 0 for various delay values.

D. Motivating case study: PATO system
In our work, we used a physical system called PATO as a motivating case study [22]. This system has a fourth-order state-space. The states of the system are the position of the two masses θ 1 and θ 2 and their respective rotary speeds of ω 1 and ω 2 . The controller input u(t) is the current i m of the motor speed controller. The output of the system y(t) is the position of the first mass θ 1 . Here, the control task is to make θ 1 follow a desired reference r(t). The identified state-space of the system is adopted from experiments reported in [23] and is as follows: E. The Impact of the delay on system zeros We illustrate the impact of delay on the system zeros with the example of system (9). We consider sampling period h = 8ms and varied delay in the range 0 ≤ D c < h. For each delay choice, we first obtain discrete-time augmented system (6) and next, we obtain the zero polynomial (8) for the given h and D c . Fig. 2 shows the number of unstable zeros for each value of D c . It shows that the system has different numbers of unstable zeros for different delays. In particular, there are four delay regions with different number of unstable zeros.
where z 3 and z 4 are unstable.
• For 1.1ms ≤ D c < 3.8ms , the number of unstable zeros increases to 3. • For 3.8ms ≤ D c < 8ms , the number of unstable zeros goes down to 1. For D c = 5ms the zeros of the system are: Sensor to actuator delay (ms) where z 1 is the only unstable zero of the system. Therefore, the number of unstable zeros of system (9) may change with the value of sensor-to-actuator delay. This further motivates us to investigate how the location of system zeros changes with sensor-to-actuator delay D c .

III. ZERO LOCI ANALYSIS
In this section, we obtain zero loci by computing system zeros from zero polynomial (as described in Subsection II-E) and their transition for 0 ≤ D c < h for a given h. Next, we provide a number of observations about the zero loci as well as its behavior for first order and second order systems. Fig. 3 and Fig. 4 show the zero loci for the system (9) with h = 8ms and h = 10ms respectively. A zero starts from the circle point for D c = 0 and moves toward the star point for D c = h− where is an infinitesimal quantity. The arrows shows the direction of transition of a zero location. The dotted line represents the unit circle.
• For h = 8ms, the analysis is the same as what is described in Section II-E. System starts with 4 stable zeros for D c = 0 but two of them (red and blue lines) immediately go out of the unit circle and become unstable for a small amount of delay (0.1ms ≤ D c < 1.1ms). By increasing the delay another zero (yellow line) also becomes unstable. For a higher delay (3.8ms ≤ D c < 8ms), two of unstable zeros (red and blue lines) come back to unit circle and become stable. • For h = 10ms, the system starts with 4 stable zeros for D c = 0 but two of them (red and blue lines) go out of the unit circle and become unstable for a small delay (0 ≤ D c < 0.3ms). The number of unstable zeros does not change for 0.3ms ≤ D c < 9ms. For delays close to the sampling period (9.0ms ≤ D c < 10ms), one of the unstable zeros (red line) comes back to the unit circle and becomes stable. It can be noted, in the above examples, there is a zero at the origin for D c = 0 which grows with the increase in delay. The existence of this zero can be proven by the following lemma.
Lemma 3.1. For any controllable LTI system (1), the delayed model of (6) has a zero at the origin of z-plane for D c =0.
Proof. Since D c = 0, from (5) we observe that Γ 1 is equal to zero. This makes φ aug to be a block diagonal matrix: Since φ aug is block diagonal, its eigenvalues are the list of eigenvalues of each block which are e Ah and 0. Since the eigenvalues of φ aug are the poles of discrete-time transfer function (7), the system has a pole at the origin and poles at eigenvalues of e Ah . For D c = 0 the transfer function should be identical to the dynamic system without delay and therefore the pole at the origin should be canceled. This implies that there should be a zero at the origin to cancel the existing pole there. Therefore, there is always a zero at the origin for D c = 0.
In summary: • Zero loci show that the location of system unstable zeros may change with sensor-to-actuator delay.
• The behavior of zero loci with delay is dependent on sampling period. • At D c = 0, the system has a zero at the origin of zplane and it grows with the delay. Whether this zero passes the unit circle and becomes unstable depends on system dynamics. We further characterize the zero loci for some specific classes of dynamic systems -first order and second order systems.

A. First order systems
We consider a strictly proper first order system. The system has one state and the state vector X in (1) is a scalar. The continuous state-space of the system is: where a, b and c are scalars. The augmented state-space based on (6) is given by: Using (8), the zero polynomial for the system (11) is given by, Solving ∆(z) = 0, we obtain the system zero at z = − Γ1 Γ0 . Based on the definition of Γ 0 and Γ 1 , the following can be observed: a (e ah−aDc − 1) monotonically decreases with the increase in D c .
a (e ah −e ah−aDc ) monotonically increases with the increase in D c . • |z| = − Γ1 Γ0 monotonically increases with the increase in D c . • The system zero will start at the origin of z-plane for D c = 0 and will grow with increase of delay. For a value of D c (near half of sampling period) it goes outside the unit circle and becomes unstable when the sampling period h is sufficiently small.

B. Second order systems
The general form of a second order system in continuoustime is given by: where b 1 , b 2 , a 1 and a 2 are the system parameters. The controllable canonical form equivalent of (13) is: The augmented discrete-time equivalent of (14) is: Using the Taylor series expansion, we have: Here, we omitted the higher order elements of the series, since they are negligible with sufficiently small sampling periods. Using (16), Γ 0 and Γ 1 are given by: Using (16) and (17) in (15), we obtain the zero polynomial from (8). Next, we analyze two cases: Case 1 with b 1 = 0: The system has no internal zero. From the zero polynomial in (8) and omitting the negligible parts, we have: We observe the following: • System has two zeros and their locations depend on D c and h. • With D c = 0, we have: ∆ 0 (z) = h 2 z 2 + h 2 z, which means the system has one zero on the unit circle and one zero at the origin. • The zero on the unit circle moves outside (becomes unstable) with the increase in the delay. The zero at the origin moves from the origin towards the unit circle. • With D c = h − we have: where is an infinitesimal quantity. It means the stable zero reaches close to unit circle but does not pass it and get unstable. Fig. 5 shows the zero locus of an example second order system. The number of unstable zeros is one for D c ∈ [0, h).
Case 2 with b 1 = 0: The system has one internal zero. From the zero polynomial in (8) and omitting the negligible parts, we have: which means that the zero polynomial ∆ 1 (z) constitutes of ∆ 0 (z) (the zero polynomial in Case 1) and more elements with b 1 . We observe the following: • System has two zeros and their locations depend on delay D c , sampling period h, and system dynamics.  • With D c = 0, we have: which implies that the system has a zero at the origin and one zero at the discrete-time equivalent of internal zero. • The zero at the origin grows with the increase in delay.
For a value of D c (dependent on system dynamics), it goes outside the unit circle and becomes unstable. • The other zero which is at the discrete-time equivalent of internal zero is not affected by the delay and stays at the same point for all delay values. Clearly, the number of unstable zeros changes depending on D c . The number of unstable zeros will be either 0 or 1. Fig. 6 shows the zero locus of an example second order system.
In this section we showed that the zero placement and the number of unstable zeros can change by varying the sensorto-actuator delay. This means that if the amount of delay be known and adjustable it could be treated as a control parameter to change the location of the system zeros. Such precise regulation of delay is possible to be implemented on predictable embedded execution platforms explained in the next section.

IV. EMBEDDED PLATFORM PROPERTIES
For an embedded control implementation, we consider a tile-based architecture that offers con?guration with multi-processors (processor tiles), interconnections through a Network-on-Chip (NoC), and memories (memory tiles) within the same platform. An example architecture is shown in Fig. 7. Each processor tile is mainly composed of a MicroBlaze soft-core processor. The monitor tile is for debugging purposes. The memory tile contains the external memory interface and controller, and the NoC provides interconnection between the tiles. To enable independent implementation, verification and execution of multiple applications, the platform offers composability by virtualizing all processors, interconnections, and memory resources [8]. First, we illustrate the platform properties and scheduling. We then define sampling period and other timing properties based on the platform scheduling. Finally, we define the sensor-to-actuator as a design parameter.

A. Application scheduling
The platform uses CoMik (Composable and Predictable Micro-kernel) to create virtual processors (VPs) that can be used as dedicated resources [8]. Each VP's utilization of the underlying physical processors and their interconnections (i.e., NoC communication) are allocated in a time-division multiplexing (TDM) manner. Using perfectly periodic TDM policies both in the processors and their interconnections, the platform achieves global synchronization with a very fine (i.e., cycle accurate) time granularity.
To achieve cycle-accurate temporal behavior, we split the TDM frame into N CoMik slots of length ω clock cycles and N partition slots (or VPs) of length ψ clock cycles. The CoMik slots enable jitter-free context switching between VPs, and the applications only execute on the VPs. An application is executed in an allocated partition slot (or VP) and is paused every time a new CoMik slot starts. Its execution is only resumed in the next partition slot assigned for the same application. The TDM frame is defined at design time with desired execution order of the VPs. The TDM period is N × (ω + ψ) clock cycles. In Fig. 8, we show a   . . .
TDM frame with N = 4 and three tasks of S:sensing, C:computation, A:actuation with execution times of Ts, Tc, and Ta respectively. The black boxes are CoMik slots while white blocks are partition slots. τ is the added delay to execution of actuation in its dedicated slot. Sensing and computation tasks always start execution at the beginning of their allocated slot.
TDM table with 4 partition slots that run sequentially and periodically.

B. Control application scheduling and sampling period
We are interested in scheduling of the control application. As described in Section II, a control application consists sensing, computation and actuation operations. Each operation is implemented as a task. We schedule these tasks in the partition slots in TDM table. To make sure that the execution of each task fits in its respective partition slot, ψ is chosen as follows: where T s , T c , and T a are execution times of sensing, computation and actuation tasks respectively 1 . The calculated T s , T c , and T a on the platform are about 1000, 2000 and 1000 clock cycles respectively. ω is chosen to be as short as possible. In the current implementation for the control application, it is set to 4096 clock cycles.

C. Sampling period
Sampling period is defined as the time period between two consecutive sensing tasks. With sensing task scheduled once in the TDM table, sampling period is given by: where F p is the frequency of the platform which is 100M hz. Fig. 8 illustrate an example of TDM D. Sensor-to-actuator delay as a parameter The sensor to actuator delay is computed as (3). The minimum of D c in our platform is achieved when control tasks scheduled in consecutive slots and their execution start at the beginning of their allocated partition slots. In this case the minimum possible value for overhead would be: Using (22) in (3), the minimum D c is given by: Considering a TDM table with 4 slots, h = 10ms, ψ, ω, and T a are about 0.04ms, 2.46ms, 0.01ms respectively. Therefore, D c,min is 5.01ms. As described in Section III, the optimal delay (denoted as as D * c ) is defined as the delay which results in the minimum number of unstable zeros and is implementable on the platform. Since D c < D c,min is not implementable in the platform, D * c ≥ D c,min . With D * c > D c,min , D c can be increased either by adding partition slots between control tasks or by adding a delay in execution of actuation in its partition slot 2 . In this case D c can be defined as: where m is the number of added slots and τ is the added delay to the execution of actuation. Fig. 8 is an example where m = 1 with an added delay τ . Therefore, by choosing the right m and τ , the delay can be adjusted to D c = D * c . Thus, this mechanism allows us to use the senor-to-actuator as a design parameter.

V. DELAY-BASED FEEDFORWARD DESIGN
In this section, we present the proposed delay-based embedded feedforward tracking controller. We use the example of system described in Section II-D.

A. Controller architecture
The designed controller is a feedback-feedforward controller. The feedback part stabilizes the system and the feedforward part is a closed-loop model-inversion to achieve accurate reference tracking. The feedback part is a statefeedback with all desired poles set to 0.9 (it can be done using any other state-of-the-art design technique). Calling the feedback part as C(z) and plant transfer function as G(z), The closed-loop transfer function is: To design the feedforward part F CL , we set F CL equals (or approximately equals) to G −1 CL . Ideally, F CL is equal to G −1 CL which makes the transfer function between reference and output y equals to 1. If the closed-loop system has unstable zeros direct inversion is not possible and it yields to unstable inversion in F CL . In this case an stable approximation inverse is used. Here, we use Zero-Phase-Error Tracking controller (ZPETC) stable approximation [18]. To design ZPETC, we first rewrite G CL as: 2 The execution of sensing and computation always starts at the beginning of their respective slots.
where ∆ s (z) is the stable zero polynomial and ∆ s (z) is the unstable zero polynomial. Now, the ZPETC controller is: whereG −1 CL (z) means approximate inverse of the closed loop. ∆ * u (z) which is a zero-phase approximation of the unstable zeros is defined as: where ∆ f u (z) is defined based on ∆ u (z). It means that if: is at the same degree of ∆ u (z) with its flipped coefficients.

B. Implementation
To design the controller, we first choose the sampling period h = 10ms. As described in previous section, the minimum delay D c , min on the platform for this h = 10ms is 5.01ms. The first step is to choose the optimal delay D * c which gives the minimum number of unstable zeros and is implementable on our platform. As described in Section III, for h = 10ms, D c < 0.3ms region does not have any unstable zero. However, D c < D c , min = 5.01 is not implementable on the platform. On the other hand, D c = D c , min results in two unstable zero while the system have only one unstable zero in the region 9ms ≤ D c < 10ms. Therefore, we choose the optimal delay which is also achievable in the platform as D * c = 9.5ms. To achieve this delay, TDM frame is configured as Fig. 8, and we set m = 1 and τ = 4.59ms.

C. Results
Validation of the design is done through an HIL (hardwarein-the-loop) implemnentation. Considering the platform in Fig. 7, we implemented the discrete-time model of the system (9) with sampling period of 100µs on processor tile 1 and the designed controller on processor tile 2. The performance metric is defined as P −1 where: The reference signal is: r(t) = sin(4πt) + sin(8πt) Fig. 9 and Fig. 10 illustrate the results of MATLAB and HIL simulations for D c = D c , min = 5.01ms and D c = 9.6ms respectively. Table. I presents the performance results. HIL implementation provides results very close to the simulation which validates the proposed method. Although for the design with D c = 9.6ms gives a higher transient error, it achieves a better performance in the steady-state compared  to the design with D c = 5.01. This is because the system has one less unstable zero with D c = 9.6ms. Discussion: We demonstrated that sensor-to-actuator delay could be treated as a design parameter. In some design scenarios, an extra delay improves the performance of the controller when the number of unstable zeros decreases. More importantly, a higher delay tolerance in the control loop relaxes the requirement on the embedded platform reducing the implementation cost at the end. In embedded implementations, it is common to share platform among multiple applications. Such relaxed timing requirement implies more processing resource for other applications (e.g. the third partition slot in Fig. 8 can be assigned other applications).

VI. CONCLUSION
In this paper, we proposed a delay-based embedded feedforward tracking controller with improved tracking performance. We demonstrated that a higher sensor-to-actuator delay does not necessarily implies a lower control performance. We have shown that increasing delay may decrease the number of unstable zeros. This in turn improves the performance for controllers using the model-inversion feedforward component. Hence, we used sensor-to-actuator delay as a design parameter. Considering a platform with predictable timing behavior, we validated our approach by HIL simulations. A possible extension of our work can be a general design flow with delay as a design parameter.