Assembly-Related Chip/Package Co-Design of Heterogeneous Systems Manufactured by Micro-Transfer Printing

Technologies for heterogeneous integration have been promoted as an option to drive innovation in the semiconductor industry. However, adoption by designers is lagging behind and market shares are still low. Alongside the lack of appropriate design tools, high manufacturing costs are one of the main reasons. Micro-transfer printing (μTP) is a novel and promising micro-assembly technology that enables the heterogeneous integration of dies originating from different wafers. This technology uses an elastomer stamp to transfer dies in parallel from source wafers to their target positions, indicating a high potential for reducing manufacturing time and cost. In order to achieve the latter, the geometrical interdependencies between source, target and stamp and the resulting wafer utilization must be considered during design. We propose an approach to evaluate a given μTP design with regard to the manufacturing costs. We achieve this by developing a model that integrates characteristics of the assembly process into the cost function of the design. Our approach can be used as a template how to tackle other assembly-related co-design issues – addressing an increasingly severe cost optimization problem of heterogeneous systems design.


I. Introduction
Heterogeneous integration is considered to be one of the main drivers for innovation in the post-Moore era. However, current production volume and market share are still low due to high manufacturing costs and a lack of appropriate design tools. Design and manufacturing of heterogeneously integrated systems is challenging: different components of such systems are designed and manufactured independently -but eventually have to work as one unit without loss of performance or resources. This urgently asks for appropriate chip/package co-design flows [1]- [3].
As heterogeneous integration is achievable via a growing number of alternative integration and packaging technologies, manufacturing decisions have a strong impact on the economic viability of a package. For example, it is difficult to estimate which packaging technology is the best as it strongly influences the design. This ultimately leads to a manufacturing-related co-design problem in which manufacturing alternatives and parameters have to be considered additionally in the design flow (Fig. 1). To illustrate and to solve this co-design problem, we exemplarily utilize a promising new assembly technology called micro-transfer printing (μTP) [4]- [7].
μTP introduces a manufacturing related stamp layout, which is strongly interrelated with the chip and package layouts. However, it is not part of the conventional design flow. The Cost Evaluation (conventional) Chip/Package Co-Design

Assembly-Related Chip/Package Co-Design
Assembly Process Package Chip A

Chip B
F ix e d T e ch n o lo g y Figure 1. In contrast to conventional chip/package co-design with a fixed target technology (top), advanced packaging technologies introduces more design choices. These require an assembly-related chip/package co-design (bottom) and, ultimately, its economical evaluation (addressed in this paper). goal is to find the combination of source, target and stamp layouts that has the lowest manufacturing costs and that meets all relevant electrical constraints. In μTP, the manufacturing costs depend on the utilization of the source and target wafers as well as on the manufacturing throughput. Both, utilization and throughput, depend on the particular layouts of source wafer, target wafer and stamp.
In our paper, we present an algorithm to determine the wafer utilization, which is crucial for addressing the described co-design problem. Our approach allows an optimization of the layouts of source, target and stamp in order to minimize the manufacturing costs of the final package. This will enable designers to fully exploit the micro-transfer printing technology and, more generally, get an understanding of assembly-related co-designs problems and their solutions. Hence, the presented approach is intended as a first step towards models that enable manufacturing-cost based evaluations of design and process parameters and their optimization.

II. Technological Background and Terminology:
Micro-Transfer Printing With regard to manufacturing of heterogeneous systems, μTP is a promising assembly technology as it combines the advantages of pick and place in terms of flexibility with the advantages of wafer-level processing in terms of high throughput. Figure 2 illustrates the μTP process with its three main constituents.
The source wafer (Fig. 2 left) carries different kinds of components (such as passive or active devices), referred to as coupons, to be integrated into a package. In order to release the coupons from the source wafer, wet chemical undercut etching is performed prior to the actual transfer process.
The target wafer (Fig. 2 right) comprises the target dies on which the coupons shall be printed. Thus, the target die serves as carrier and is therefore usually the largest component of the resulting package (e.g., a CMOS circuit). Typically, an adhesion layer is deposited on the target wafer before printing. The target wafer does not require a special treatment with regard to separation as it will undergo conventional wafer cutting.
The μTP process utilizes a micro-structured elastomer stamp ( Fig. 2 top), capable to pick and transfer a huge number of elements (> 10,000) from the source to the target wafer. The printing process is based on van der Waals forces between the coupons and the stamp. The pickup and release process can be controlled due to a stamping-speed depending adhesion between the coupons and the stamp. During a fast movement of the stamp, its adhesion is larger than the bonding with the wafer, and vice versa. Depending on the size and the layout of the stamp, not all coupons and/or target dies are accessible. The degree of which a wafer can be accessed by the stamp is called wafer utilization.
The μTP process ends with the placement of the coupons, followed by processing steps on wafer-level, such as the creation of electrical interconnects via a redistribution layer (RDL).
The main benefits of μTP are as follows: substrate-based as well as substrate-less stacking of heterogeneous components on package-level; coupons and target dies as well as the wafers can be of arbitrary sizes; highly parallelized transfer process, with the option of stemming from multiple source wafers; subsequent processing on wafer-level.
On the other hand, as discussed in Section I, the co-design becomes assembly-related, and thus, more challenging. The new layout dependencies between source, target and stamp have to be considered -focusing on their strong impact on manufacturing costs.

III. Preliminaries
This section provides the reader with the background information needed to understand our focus on the determination of the wafer utilization presented in Section IV.

A. Assembly-Related Chip/Package Co-Design
During an assembly-related chip/package co-design, not only the parameters of the chip and package designs (e.g., schematics and layouts) are optimized. Also manufacturing related options, such as the stamp layout in μTP, need to be considered.
Irrespective of whether the parameters are determined with the aid of an optimization procedure or are specified manually, the evaluation of each solution must be possible in order to make credible design decisions. Usually, such an evaluation is implemented by a cost function combining one or more cost criteria, such as manufacturing costs. The μTP design example in Fig. 3 is based on a certain set of parameters, such as the layouts of the coupon, the target die, and the stamp. However, in order to evaluate the manufacturing costs, it is essential to know the utilization of the source and target wafers, which is not a direct cost parameter.

B. Cost Model
The following cost model focuses on manufacturing costs and is used to motivate the modeling of assembly-related processes (in our case μTP). This model is simplified for better comprehensibility and therefore ignores technological details, such as the required changeover times (for stamp or wafer exchange in the printing tool). In the following, n x stands for "number of x" and costs x gives the "costs of x". n Stampings = n Quantity /n DiesPerStamp costs Die = (n TargetWafers · costs TargetWafer )/n Quantity costs Coupon = (n SourceWafers · costs SourceWafer )/n Quantity costs μTP = costs MachineHour · t StampingDuration · n Stampings costs PU = costs Die + n CouponsPerDie · costs Coupon + costs μTP The final costs are the costs per package unit (costs PU ). They are made up of the costs per die, the costs of the coupons placed on a die and the μTP manufacturing costs. Directly considered are: design parameters (n DiesPerStamp , n CouponsPerDie ), economic parameters (n Quantity , costs SourceWafer , costs TargetWafer , costs MachineHour ) and technological parameters (t StampingDuration ). However, the derived parameters n SourceWafers and n TargetWafers are not easy to compute, as they depend on the expected wafer utilization which itself depends on the wafer and stamp layouts. The cost calculation of a particular system design is hardly Furthermore, the cost equation depicts the trade-off between the stamp size (and thus, high throughput) and the number of required wafers to reach the production target (i.e., the larger the stamp, the less stampings are required, but the lower the expected utilization will be). A reduced wafer utilization can increase manufacturing costs significantly.
To apply μTP in an economically efficient manner, the optimization of stamp size and layout is required. As the wafer utilization is difficult to describe analytically, we need an appropriate heuristic as presented in the following sections.

C. Problem Formulation
As motivated above, our goal is to provide a heuristic to determine wafer utilization of a given stamp and wafer combination. Essentially, we need to find an optimal set of stamping positions in such a way that those positions are valid and the number of picked coupons from a wafer is maximized. The corresponding algorithm is described in Section IV and works with the abstractions outlined next.
As the stamp and the (source) wafer have identical grid and element sizes, the wafer utilization can be determined independently of these parameters; only the relative layouts of the elements matter. Thus, the wafer and stamp layouts, which are required as input to the algorithm, can be reduced to discretized matrices as illustrated in Figure 4.
Basically, each element in the layout corresponds to an entry in a matrix M r,c = (m i, j ), where the rows and columns represent the layout grid. An entry m i, j has the corresponding layout position (x, y) = (( j − 1) · pitch x , (i − 1) · pitch y ). We set m i, j = 1 if an element exists at that position (e.g., a coupon on the source wafer), m i, j = 0 if there is no element at that position, and m i, j = 2 if the element is "picked" (relevant for wafers only). The layout coordinates originate at the top left with x increasing in positive horizontal direction and y increasing in negative vertical direction. The utilization can be easily determined by counting the picked elements in M r,c .
Throughout the paper, the following assumptions and simplifications are made: the target die pitch is a multiple of the source wafer pitch; each stamp needs to be fully populated; usage of a single stamp only (i.e., no repair steps, no stamp combinations); wafer layouts do not contain any auxiliary structures (e.g., alignment markers, test structures); no consideration of known good die or yield models.

IV. Algorithm for Estimating the Stamp Utilization
The optimization of the stampings on a wafer to maximize utilization is NP-hard (see Sec. IV-A4). Hence, we need an appropriate heuristic to estimate the wafer utilization. Figure 5 illustrates the stamp utilization process. Input data are the wafer layout (Fig. 5a) and the stamp layout (Fig. 5b). Basically, the provided layout data is reduced to a Maximum Independent Set (MIS) problem and (heuristically) solved by KaMIS, a third party MIS solver [8]. The algorithm outputs the utilization of the wafer (Fig. 5g) and is divided into the following five steps (enumeration as in Fig. 5):

A. Algorithm Description
1) Determination of Valid Stamp Positions: The first step is to identify all valid stamp positions (Fig. 5c). In our current setup we assume only fully populated stamps as valid1. Valid positions are derived from a "simulated" application of the stamp on the wafer. Note that the resulting stamp positions may have negative indices with regard to the wafer matrix.
First, we create two sets W and S containing all wafer and stamp elements, respectively. Based on W and S, the valid stamp indices V are obtained.
2) Identify Stamp Implications: In order to find out how a stamping on one particular position v m ∈ V invalidates other positions, we analyze S and obtain the first order dependencies. A stamp on a position v m would pick some elements from the wafer. In consequence, a stamp position v n which also requires one of these already-"picked" elements is related to v m . We store these directed dependencies within another set D, which contains the affected positional offsets (Fig. 5d). Note the point reflection of the resulting (directed) dependency offsets. Since we will target undirected relations between each stamp position in the next step, this symmetry can be used to reduce the number of offsets by half.

3) Building the Stamp Dependency Graph:
Based on D and V we derive a graph which represents the dependencies between different stamp positions (Fig. 5e). Each node in this graph maps to one valid stamping position. If a stamp dependency between two positions exists, an edge is inserted between the two corresponding nodes.

4) Solving the Maximum Independent Set Problem:
In order to get the maximum number of stampings on the wafer, we need to identify the maximum number of independently selectable nodes in G (i.e., all selected nodes must not share a single edge, Fig. 5f). This NP-hard problem, known as a maximum independent set (MIS) problem, is solved by applying KaMIS, a solver for the MIS problem [8]. As result, KaMIS returns the desired maximum independent set.

the maximum number of elements 5) Apply Stampings on Wafer:
With V MIS available, it is straightforward to apply the corresponding stampings on the wafer (Fig. 5g). For each element position on the stamp, the respective stamp position offset is applied.

B. Adaptation to Target Wafer
The presented algorithm can be applied directly to obtain the source wafer utilization as each element on the stamp directly corresponds to an element on the source wafer. In contrast, the target wafer utilization can not be calculated directly with the presented algorithm; instead, a slight modification is required. Specifically, we need to create a virtual "target wafer stamp" on which the element grid corresponds to the target wafer grid. Figure 6 illustrates the conversion. A given (source) stamp is partitioned corresponding to the source wafer grid (cf. Fig. 6a). In consequence of the μTP process, the stamp also shows an implicit second order pattern (i.e., the repeating target die layout). This can be seen in Fig. 6b where two coupons are placed on each target die. These sub-layouts result in a new (target die) grid which yields the required "target wafer stamp" (cf. Fig. 6c).
If this derived stamp is used in combination with the target wafer layout as input, the presented algorithm determines the target wafer utilization.

V. Summary and Outlook
In this paper we used the new μTP technology to illustrate the interdependencies between design and manufacturing in order to introduce assembly-related chip/package co-design. Specifically, we developed a model of the assembly process (wafer utilization) to evaluate design decisions (stamp and wafer layout) with regard to their impact on manufacturing cost.
In contrast, conventional chip/package co-design typically is limited to a single integration technology. Hence, it is not suitable for design problems that consider different assembly variants. Such a comparison requires models of the assembly processes integrated into the design tools. The presented model is a first step towards such an integration. It enables manufacturing-cost-based evaluations of design and process parameters and their optimization.
In the future, we will employ this new approach in a codesign flow in order to find optimized die dimensions, source and target wafer layouts, and stamp designs with regard to manufacturing cost. Furthermore, we plan to extent our tool in order to support stamps of different sizes, which will further reduce cost of heterogeneous systems manufactured using the μTP technology.