Conference paper Open Access

Time-division Multiplexing Automata Processor

Jintao Yu; Hoang Anh Du Nguyen; Muath Abu Lebdeh; Mottaqiallah Taouil; Said Hamdioui


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  <identifier identifierType="DOI">10.5281/zenodo.2533075</identifier>
  <creators>
    <creator>
      <creatorName>Jintao Yu</creatorName>
      <affiliation>Laboratory of Computer Engineering, Delft University of Technology, Delft (NL)</affiliation>
    </creator>
    <creator>
      <creatorName>Hoang Anh Du Nguyen</creatorName>
      <affiliation>Laboratory of Computer Engineering, Delft University of Technology, Delft (NL)</affiliation>
    </creator>
    <creator>
      <creatorName>Muath Abu Lebdeh</creatorName>
      <affiliation>Laboratory of Computer Engineering, Delft University of Technology, Delft (NL)</affiliation>
    </creator>
    <creator>
      <creatorName>Mottaqiallah Taouil</creatorName>
      <affiliation>Laboratory of Computer Engineering, Delft University of Technology, Delft (NL)</affiliation>
    </creator>
    <creator>
      <creatorName>Said Hamdioui</creatorName>
      <affiliation>Laboratory of Computer Engineering, Delft University of Technology, Delft (NL)</affiliation>
    </creator>
  </creators>
  <titles>
    <title>Time-division Multiplexing Automata Processor</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2019</publicationYear>
  <subjects>
    <subject>time-division multiplexing</subject>
    <subject>automata</subject>
    <subject>parallel processing</subject>
  </subjects>
  <dates>
    <date dateType="Issued">2019-01-07</date>
  </dates>
  <language>en</language>
  <resourceType resourceTypeGeneral="Text">Conference paper</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/2533075</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsVersionOf">10.5281/zenodo.2533074</relatedIdentifier>
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  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode">Creative Commons Attribution Non Commercial No Derivatives 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.&lt;/p&gt;</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/780215/">780215</awardNumber>
      <awardTitle>Computation-in-memory architecture based on resistive devices</awardTitle>
    </fundingReference>
  </fundingReferences>
</resource>
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