Conference paper Open Access

Time-division Multiplexing Automata Processor

Jintao Yu; Hoang Anh Du Nguyen; Muath Abu Lebdeh; Mottaqiallah Taouil; Said Hamdioui


Citation Style Language JSON Export

{
  "publisher": "Zenodo", 
  "DOI": "10.5281/zenodo.2533075", 
  "language": "eng", 
  "title": "Time-division Multiplexing Automata Processor", 
  "issued": {
    "date-parts": [
      [
        2019, 
        1, 
        7
      ]
    ]
  }, 
  "abstract": "<p>Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.</p>", 
  "author": [
    {
      "family": "Jintao Yu"
    }, 
    {
      "family": "Hoang Anh Du Nguyen"
    }, 
    {
      "family": "Muath Abu Lebdeh"
    }, 
    {
      "family": "Mottaqiallah Taouil"
    }, 
    {
      "family": "Said Hamdioui"
    }
  ], 
  "type": "paper-conference", 
  "id": "2533075"
}
57
40
views
downloads
All versions This version
Views 5757
Downloads 4040
Data volume 25.1 MB25.1 MB
Unique views 5151
Unique downloads 3838

Share

Cite as