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Hardware Synthesis of Weakly Consistent C Concurrency

Nadesh Ramanathan; Shane Fleming; John Wickerson; George Constantinides


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{
  "conceptrecid": "702959", 
  "created": "2016-12-19T19:21:46.914353+00:00", 
  "doi": "10.5281/zenodo.200339", 
  "id": 200339, 
  "links": {
    "badge": "https://zenodo.org/badge/doi/10.5281/zenodo.200339.svg", 
    "doi": "https://doi.org/10.5281/zenodo.200339"
  }, 
  "metadata": {
    "access_right": "open", 
    "access_right_category": "success", 
    "creators": [
      {
        "affiliation": "Imperial College London", 
        "name": "Nadesh Ramanathan"
      }, 
      {
        "affiliation": "Imperial College London", 
        "name": "Shane Fleming"
      }, 
      {
        "affiliation": "Imperial College London", 
        "name": "John Wickerson"
      }, 
      {
        "affiliation": "Imperial College London", 
        "name": "George Constantinides"
      }
    ], 
    "description": "<p>Hardware Synthesis of Weakly Consistency C Concurrency</p>\n\n<p>This webpage contains additional material for the paper Hardware Synthesis of Weakly Consistent C Concurrency (FPGA17paper.pdf).\u00a0</p>\n\n<p>Contents</p>\n\n<ol>\n\t<li>Verifying that our scheduling constraints implement the C11 standard</li>\n\t<li>Verifying the lock-free circular buffer</li>\n\t<li>Motivating examples</li>\n\t<li>Experimental Data</li>\n</ol>\n\n<p>1. Verifying that our scheduling constraints implement the C11 standard</p>\n\n<p>As explained in Section 4.4, we have used the Alloy tool to verify that our scheduling constraints are sufficient to implement the memory consistency model defined by the C11 standard. In alloy.zip, we provide the Alloy model files that we used. The first four are taken from Wickerson et al.'s work on comparing memory consistency models; the fifth is new.</p>\n\n<ul>\n\t<li>relations.als contains helper functions.</li>\n\t<li>exec.als encodes general program executions.</li>\n\t<li>exec_C.als encodes C11 program executions.</li>\n\t<li>c11.als encodes the constraints imposed by the C11 memory consistency model.</li>\n\t<li>question.als encodes our scheduling constraints, and several queries for checking that these scheduling constraints are strong enough to enforce the constraints required by the C11 memory consistency model.</li>\n</ul>\n\n<p>To reproduce our result, save the five files above into the same directory, download Alloy, open question.als in Alloy, and run the queries contained within.</p>\n\n<p>2. Verifying the lock-free circular buffer</p>\n\n<p>As explained in Section 5.1, we have used the CppMem tool to verify that our case-study application, a lock-free circular buffer, is free from data races. In order to make the verification feasible, we removed the while-loop, replaced the array variable with a scalar, removed some unimportant local variables, and simplified the increment function. Below, we give the actual code that we verified.<br>\n<br>\nint main() {<br>\n\u00a0 atomic_int tail = 0;<br>\n\u00a0 atomic_int head = 0;<br>\n\u00a0 int arr = 0;<br>\n\u00a0 {{{ {<br>\n\u00a0 \u00a0 int chead = head.load(memory_order_acquire);<br>\n\u00a0 \u00a0 int ctail = tail.load(memory_order_relaxed);<br>\n\u00a0 \u00a0 if (ctail+1 != chead) {<br>\n\u00a0 \u00a0 \u00a0 arr = 42;<br>\n\u00a0 \u00a0 \u00a0 tail.store(ctail+1, memory_order_release);<br>\n\u00a0 \u00a0 }<br>\n\u00a0 } ||| {<br>\n\u00a0 \u00a0 int ctail = tail.load(memory_order_acquire);<br>\n\u00a0 \u00a0 int chead = head.load(memory_order_relaxed);<br>\n\u00a0 \u00a0 if (ctail != chead) {<br>\n\u00a0 \u00a0 \u00a0 arr;<br>\n\u00a0 \u00a0 \u00a0 head.store(chead+1, memory_order_release);<br>\n\u00a0 \u00a0 }<br>\n\u00a0 } }}}<br>\n\u00a0 return 0;<br>\n}</p>\n\n<p>To reproduce our result, paste the code above into CppMem's web interface and click Run. The tool should report (after a couple of minutes) that the code has 92 candidate executions, of which two are consistent, neither of which exhibit data races.</p>\n\n<p>3. Motivating Examples</p>\n\n<p>We provide the actual code that displays coherence and message-passing violation in motivating-examples.zip, as described in Section 2 of our paper. These examples have been tested and verified on LegUp's VM. For convenience, we have included the output logs of each experiment for viewing. We include a \"transcript\" of the execution and a schedule trace, which can be visualised using LegUp's scheduleviewer.</p>\n\n<p>4. Experimental Data</p>\n\n<p>We also provide the raw experiment data from Section 5 of our paper. We conduct two experiments, for which we provided raw data on all seven\u00a0design points.</p>\n\n<ul>\n\t<li>chaining.csv contains the raw data for the chaining experiment.</li>\n\t<li>bursting.csv contains the raw data for the bursting experiment.</li>\n\t<li>The version number are from 1 to 7 for Unsound, SC, OMP criticals, SC atomics, Weak atomics, Mutexes and OMP atomics respectively.</li>\n</ul>", 
    "doi": "10.5281/zenodo.200339", 
    "keywords": [
      "atomic operations, C/C++, FPGAs, high-level synthesis, lock-free algorithms, memory consistency models, scheduling"
    ], 
    "license": {
      "id": "CC-BY-4.0"
    }, 
    "publication_date": "2016-12-02", 
    "relations": {
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    "resource_type": {
      "title": "Dataset", 
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    }, 
    "title": "Hardware Synthesis of Weakly Consistent C Concurrency"
  }, 
  "owners": [
    26464
  ], 
  "revision": 2, 
  "updated": "2017-05-30T04:31:18.143230+00:00"
}

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