10.5281/zenodo.165812
https://zenodo.org/records/165812
oai:zenodo.org:165812
Fernandez, Gabriel
Gabriel
Fernandez
Universitat Politecnica de Catalunya and also with the Barcelona Supercomputing Center
Jalle, Javier
Javier
Jalle
Universitat Politecnica de Catalunya and also with the Barcelona Supercomputing Center
Abella, Jaume
Jaume
Abella
Universitat Politecnica de Catalunya and also with the Barcelona Supercomputing Center
Quinones, Eduardo
Eduardo
Quinones
Universitat Politecnica de Catalunya and also with the Barcelona Supercomputing Center
Vardanega, Tullio
Tullio
Vardanega
University of Padua, Italy
Cazorla, Francisco J.
Francisco J.
Cazorla
Barcelona Supercomputing Center, Spanish National Research Council (IIIA-CSIC)
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration
Zenodo
2016
2016-10-11
10.1109/TC.2016.2616307
10.5281/zenodo.165993
https://zenodo.org/communities/safure_h2020
https://zenodo.org/communities/eu
Creative Commons Attribution 4.0 International
Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which a processor resource may serve an incoming request, when its access is arbitrated using time-predictable policies such as round-robin or FIFO. We call this value upper-bound delay (ubd). Deriving trustworthy ubd statically is possible when sufficient public information exists on the timing latency incurred on access to the resource of interest. Unfortunately however, that is rarely granted for commercial-of-the-shelf (COTS) processors. Therefore, the users resort to measurement observations on the target processor and thus compute a "measured" ubdm. However, using ubdm to compute worst-case execution time values for programs running on COTS multicore processors requires qualification on the soundness of the result. In this paper, we present a measurementbased methodology to derive a ubdm under round-robin (RoRo) and first-in-first-out (FIFO) arbitration, which accurately approximates ubd from above, without needing latency information from the hardware provider. Experimental results, obtained on multiple processor configurations, demonstrate the robustness of the proposed methodology.
European Commission
10.13039/501100000780
644080
SAFety and secURity by design for interconnected mixed-critical cyber-physical systems