Preprint Open Access

A phase-change memory model for neuromorphic computing

S. R. Nandakumar; Manuel Le Gallo; Irem Boybat; Bipin Rajendran; Abu Sebastian; Evangelos Eleftheriou


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  <identifier identifierType="URL">https://zenodo.org/record/1492261</identifier>
  <creators>
    <creator>
      <creatorName>S. R. Nandakumar</creatorName>
      <affiliation>IBM Research—Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland; New Jersey Institute of Technology, Newark, New Jersey 07102, USA</affiliation>
    </creator>
    <creator>
      <creatorName>Manuel Le Gallo</creatorName>
      <affiliation>IBM Research—Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland</affiliation>
    </creator>
    <creator>
      <creatorName>Irem Boybat</creatorName>
      <affiliation>IBM Research—Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland; Ecole Polytechnique Federale de Lausanne, 1015 Lausanne, Switzerland</affiliation>
    </creator>
    <creator>
      <creatorName>Bipin Rajendran</creatorName>
      <affiliation>New Jersey Institute of Technology, Newark, New Jersey 07102, USA</affiliation>
    </creator>
    <creator>
      <creatorName>Abu Sebastian</creatorName>
      <affiliation>IBM Research—Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland</affiliation>
    </creator>
    <creator>
      <creatorName>Evangelos Eleftheriou</creatorName>
      <affiliation>IBM Research—Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland</affiliation>
    </creator>
  </creators>
  <titles>
    <title>A phase-change memory model for neuromorphic computing</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2018</publicationYear>
  <dates>
    <date dateType="Issued">2018-10-17</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Preprint</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/1492261</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1063/1.5042408</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode">Creative Commons Attribution Non Commercial No Derivatives 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;Phase-change memory (PCM) is an emerging non-volatile memory technology that is based on the reversible and rapid phase transition between the amorphous and crystalline phases of certain phase-change materials. The ability to alter the conductance levels in a controllable way makes PCM devices particularly well-suited for synaptic realizations in neuromorphic computing. A key attribute that enables this application is the progressive crystallization of the phase-change material and subsequent increase in device conductance by the successive application of appropriate electrical pulses. There is significant inter- and intra-device randomness associated with this cumulative conductance evolution, and it is essential to develop a statistical model to capture this. PCM also exhibits a temporal evolution of the conductance values (drift), which could also influence applications in neuromorphic computing. In this paper, we have developed a statistical model that describes both the cumulative conductance evolution and conductance drift. This model is based on extensive characterization work on 10 000 memory devices. Finally, the model is used to simulate the supervised training of both spiking and non-spiking artificial neuronal networks.&lt;/p&gt;</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/780215/">780215</awardNumber>
      <awardTitle>Computation-in-memory architecture based on resistive devices</awardTitle>
    </fundingReference>
  </fundingReferences>
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