Dual Edge-Triggered D-Type Flip-Flop with Low Power Consumption

In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.


INTRODUCTION
Flip-flops are the basic storage elements used in synchronous digital VLSI circuits and in other digital electronic circuits. Edge-triggered flip-flops are often used to operate in selected sequences during recurring clock intervals to sample and hold data. Edge-triggered flip-flop circuits may be classified into one of two types. The first type latches data either on the rising or the falling edge of the clock cycle is so-called single edge-triggered flip-flop (SETFF). A conventional SETFF is triggered either at the rising edge or the falling edge of a clock cycle. This configuration is inefficient as half of the clock edges being unused, data flow tends to be slow. The other type is dual edge-triggered flip-flop (DETFF), which can operate at half of the clock frequency while maintaining the same data throughput compared to SETFF [1]. As a result, power consumption is reduced, making DETFFs desirable for low power applications [2]- [19]. There are several ways to implement a dual edge-triggered flip-flop. Among them, the most common one is to duplicate the pathway to enable the flip-flop to sample and hold data on every clock edge. However, the implementation of conventional static DETFF needs many transistors and spends too much area [20]. Furthermore, a clock chain is required to produce the correct timing that enables the DETFF circuit to function; this requirement increased the total power consumption of the design.
where P sw is the switching power, P sc is the short-circuit power, P leakage is the leakage power, and P static is the static power. In general, the switching power component usually dominates, and may account for more than 90% of the total power [3]- [6]. Further, α denotes the transition activity factor. Vs is the voltage swing, where in most cases it is the same as the supply voltage V DD . C L is the node capacitance, f ck is the clock frequency. Although the clock frequency is determined by the system specifications, the usage of DETFFs can reduce the clock frequency to half of its original value for the same data throughput. As a result, power consumption is reduced, making DETFFs desirable for low power applications [3]. As can be seen from this equation, a decrease in the capacitance on the clock line will decrease the power consumption of the clock line.
In order to reduce the complexity of circuit design, a large proportion of digital circuits are synchronous circuits; that is, they operate based on a clock signal. Among the more popular synchronous digital circuits are edge-triggered D-type flip-flops. The total clock related power consumption in synchronous VLSI circuits can be divided into three major factors: power consumption in the clock network, power consumption in the clock buffers, and power consumption in the D-type flip-flops [9]. It is worth noting that the frequency at which synchronous devices are able to operate has been limited by clock skew. The greater the frequency of the clock, the smaller the clock skew must be kept to maintain synchronization of the device. It has been observed that clock skew decreases as capacitance on the clock line is decreased. Thus, reducing capacitance on the clock line may allow synchronous circuits to operate at higher clock frequencies. Therefore, the improvement of such flip-flops circuits a decreasing in power consumption, without impairing other characteristics, is of prime importance to the VLSI industry. Though several contributions have been made to the art of DETFFs, a need evidently occurs for a design that still further improves the relative power consumption of DETFFs.
The remainder of this paper is organized as follows. Section II presents a brief description of existing DETFFs. The proposed DETFF is described in Section III. The simulation results and a comparison between the existing DETFFs and the proposed DETFF in terms of power consumption and power-delay-products are discussed in Section IV. Last section is a conclusion and summary for the paper.

EXISTING DUAL EDGE-TRIGGERED FLIP-FLOPS
There are several DETFFs have been proposed [2]- [19]. Among them, some DET D-type flipflops have been presented by Unger [2]. Even though the flip-flops described in his paper are faster compared with some SETFFs, their complex design has made it undesirable. Gago et al. [3] presented a static DET master-slave flip-flop. The design duplicates a SETFF but shares the clock transistors that are common to both latches. These implementations suffer from a larger clock load at the same level of performance as a SETFF. Hossain et al. [4] proposed a static DETFF which including a 16-transistor arranged in a parallel configuration. The design also comprises two latches, each of which has a loop within itself for maintaining charge levels for providing static functionality. The loops are isolated from each other. Blair [5] provided a static DET design and a semi-static DET design. The static DET design is a modified version of Hossain's static design. Varma et al. [6] provided a static DET design and a dynamic DET design. This includes a 16-transistor CMOS implementation of the static design in which the availability of an inverted clock is assumed. The design requires two more transistors if the clock is to be inverted locally.
The flip-flop DET pedram proposed in [7] is illustrated in Fig. 1. To reduce the overall transistor count as well as the load on the clock signal, two pass transistors are employed in the feedback portion instead of transmission gates. This results in reducing the driving capability of the succeeding stages and causing DC power consumption in the output inverter. Fig. 2 shows the circuit implementation of DET llopis proposed in [8]. There is made unidirectional on the data paths, which is a modified version of the DETFF proposed in [4]. Complementary logic gates are employed to balance the output rise and fall times of the original DETFF. Advantageously, the usage of DETFFs leads to a reduction of 50% in power consumption of the clock network, and a reduction of up to 45% in the power consumption inside the flip-flops. However, the area and delay penalties are rather large.  Strollo et al. [9] proposed a low power DETFF using a single latch, DET Strollo , shown in Fig. 3. The operation of DET Strollo is highly dependent on the internal clock buffer sizing and the propagation delay of the internal clock buffers. It compares the input data D to output data Q and according to the comparison will disable those unnecessary clock switching. More particular for this clock-gating scheme, whenever the comparator detects the change at the input, the gated clock signal will generate a pulse. Otherwise, the gated clock signal maintains logic high. If this clock-gating scheme is used on the DETFF, then the flip-flop will be triggered twice for every Electronic copy available at: https://ssrn.com/abstract=3278480 data transition, which causes extra power consumption. DET Strollo uses only eight MOS devices in addition to the clock driver, and hence requires a small silicon area. Another DETFF illustrate in Fig. 4, DET chung , is proposed by Chung et al. in [10], which comprises two differential SETFFs connected in parallel. The data path is duplicated. Both SETFFs have a pair of cross-coupled inverters as the master stage and a tri-state inverter as the slave stage, respectively. The left data path samples data when CLK=1, the right data path samples data when CLK=0. The main advantage of this design is the ability to avoid stacking PMOS transistors over NMOS transistors, and the prevention of floating nodes. However, a relatively large crossover current exists in the internal nodes, causing significant delays and high power consumption [11].  As shown above, a problem with static flip-flop circuits is a requirement for more than one clock signal. Usually, a clock chain is required to produce the correct timing that enables the circuit to function. This requirement increased the total power consumption of the design. In order to overcome the problem of distributing several clock signals and avoid the serious problems caused by clock skew, only one clock signal is employed in the proposed DETFF design.

PROPOSED DUAL EDGE-TRIGGERED FLIP-FLOP
The proposed DET D-type flip-flop is illustrated in Fig. 5. The proposed DETFF is composed of six pass transistors, two latches, and an output keeper circuit. Among them, the latches are respectively constructed by back-to-back configuration of inverters I1, I2 and inverters I3, I4; the output keeper circuit is formed by inverter I5 and regenerative transistor MP4. In the output near the supply voltage VDD when output terminal Q is at logic low. This design also can be thought of as a parallel structure which similar to that of DET chung . Similarly, two differential master-slave flip-flops connected in parallel and each of flip-flop utilizes differential data signals at the master stage. As shown in Fig. 5, master latch can be further divided into sample portion and hold portion. The sample portion of the latch receives the differential data signals and passes them to the hold portion responsive to a control signal. However, the hold portion stores and outputs the differential data signals. In more detail, in the upper data path, the sample portion is for providing the differential data signals to hold portion when the clock signal is at logic high. The hold portion is for storing the differential data signals it receives from sample portion. A clock signal CK is provided to the gate terminal of both transistors MN1 and MN2. When the clock signal is at logic high, both transistors MN1 and MN2 are turned on. Conversely, when the clock signal is at logic low, both transistors MN1 and MN2 are turned off. The clock signal thus selects when the data signal D and the inverted data signal DB are passed to hold portion. The back-to-back configuration of inverters I1 and I2 stores the data signal D and the inverted data signal DB which are passed to hold portion. Finally, node N1 and node N2 provide the inverted data signal and the data signal, respectively, stored in hold portion. Besides, in the lower data path, master latch is essentially the same as that of the upper data path previously described, except transistors MP1 and MP2 are provided in place of transistors MN1 and MN2, respectively. Thus, sample portion provides the differential data signals to hold portion when the clock signal is at logic low. It is worth noting that, in this design, each data line in the sample portion comprises a single pass transistor for selectively passing one of the differential data signals responsive to the control signal, unlike that of DET chung which a tristate inverter is used.
Electronic copy available at: https://ssrn.com/abstract=3278480 Next, the operation of the proposed DETFF circuit will be explained as follows. When the clock signal CK is at logic low, transistors MP1, MP2, MP3 are turned on and transistors MN1, MN2, MN3 are turned off. The inversed signal of input signal D and the input signal DB are quickly conducted into the node N3 and hold by the latch constructed by inverters I3 and I4. Meanwhile, the previously hold data in node N1 is quickly pass to the output terminal Q with the help of transistor MP3. If the voltage level of the output terminal Q is at logic low, node N5 goes logic high with the help of regenerative transistor MP4. Node N5 remains high as long as the output terminal Q is at logic high. On the contrary, when the clock signal CK is changed from logic low to logic high, transistors MN1, MN2, MN3 are turned on and transistors MP1, MP2, MP3 are turned off. Because MN1 and MN2 are turned on and MP3 is turned off, the inversed signal of input signal D and the input signal DB are temporarily stored in the node N1 and hold by the latch constructed by inverters I1 and I2. Meanwhile, the data signal stored in node N3 output to the output terminal Q via transistor MN3. Furthermore, if the voltage level of the output terminal Q is at logic low, the storage node N5 will be pulled up to a logic high via regenerative transistor MP4. Therefore, when the clock makes a inverse transition, the role of upper pathway and lower pathway is exchanged, exhibiting alternative sampling and transporting behaviour.

SIMULATION AND RESULTS
Several metrics are available for analysis of VLSI circuits, such as the delay from data to the output (t dq ), the total power consumption (P total ), the power-delay product (PDP dq ), and the energy-delay product (EDP dq ). In the section, simulations are performed to examine the performance and merit of the proposed DETFF.

TESTBENCH
The testbench for this paper is illustrated in Fig. 6 [8]. The input buffers are used to provide realistic data and clock signals. A fanout of five inverters is used as the nominal load for each DETFF. These inverters, in turn, drive a capacitive load C L of 25 fF each, to simulate the loading from the previous logic stages, as well as the following stages. The total power consumption is composed of three components: local data power consumption, local clock power consumption, and internal power consumption. It is worth noting that the clock power consumption is determined solely by the clock load of the flip-flop, whereas the distribution of the internal and data power consumption is affected by the structure and operation of the latching element itself as well as the input switching activity [10].

SIMULATION RESULTS AND DISCUSSION
This subsection presents the simulation results of power consumption of the proposed DETFF with four previously DETFFs discussed in section 2, under different data activities and different data rates, respectively. To evaluate the performance of the proposed DETFF, other designs are simulated under similar conditions. All simulations are carried out using a 0.18 um CMOS technology at nominal conditions: VDD=1.8V and at room temperature. Fig. 7 illustrates the Electronic copy available at: https://ssrn.com/abstract=3278480 simulated analysis waveform of the proposed DETFF. During this simulation, a data activity of 0.5 and a data rate of 500 Mbits/sec are assumed.  Table 1 illustrates a comparison among different metrics for various DETFFs are performed, based on the same conditions as above. As shown in Table 1, it appears that DET pedram consumes the most power, due to an extensively large internal and data power consumption. DET strollo has the longest delay. This also leads to the maximum energy consumption. DET proposed consumes the least power and has the minimum delay, hence the least energy. Compared to the previously proposed DETFFs, the power reduction of this work has 26.60%, 53.63%, 16.75%, and 24.67%, respectively. In general, the power-saving of using DETFF is strongly dependent on data activity α [20].
Therefore, it is desirable to simulate various DETFFs with different data activities. Table 2 demonstrates the power consumption of various DETFFs at different data activities. Also, the relationship of power consumptions versus different data activities is illustrated in Fig. 8. It can be seen that the power consumption increases with the increasing in data activity because the power consumption is proportional to the data activity. For example, in the case of applications with data activity 1 α = , exhibit the largest total power consumption.
However, one exception is DET pedram , in which the data sequence consists of all 0's, the power consumption is remarkably large. On the other hand, for the case of all 1's, the power consumption is especially small, whereas the data power is notably larger. Furthermore, the total power consumption of DET llopis is very close to DET chung in all data activities. In addition, one Electronic copy available at: https://ssrn.com/abstract=3278480 finds that DET proposed represents a significant power reduction over four previously reported DETFFs under different data activities, except in the case of 1 α = , in which it exhibits a substantially more internal power consumption.  In the following, four previously reported DETFFs along with the proposed DETFF are analysed for their power consumptions at varying data rates. The power consumptions of various DETFFs under different data rates, for different data activities, are depicted in Tables. 3-5. Table 3 indicates the power consumption at different data rates for data activity α= 0.  Figure 9 is a curve of power consumption versus data rates for Table 3. As can be seen from this figure, DET pedram consumes the most power for all data rates. Further, the total power consumption of DET llopis is very close to that of DET chung for all data rates. In addition, the proposed flip-flop DET proposed has the least power consumption among all the designs for all data Electronic copy available at: https://ssrn.com/abstract=3278480 rates. Finally, it is indicated that the proposed DET proposed has up to 86.87% power-saving compared with that of DET pedram for data rate is 2000 Mbits/s.   Figure 10. Power consumption dependence on data rates for data activity α= 0.5. Table 4 indicates the power consumption at different data rates for data activity α= 0.5. Figure 10 is a curve of power consumption versus data rates for Table 4. From Table 4, one finds that the proposed DET proposed represents a significant power-saving over four previously reported DET Electronic copy available at: https://ssrn.com/abstract=3278480 flip-flops. As can be seen from Fig. 10, DET pedram consumes the most power for all data rates. Further, the total power consumption of DET llopis is very close to that of DET chung for all data rates. In addition, the proposed flip-flop DET proposed has the least power consumption among all the designs for all data rates. Finally, it is indicated that the proposed DET proposed has up to 88.73% power-saving compared with that of DET pedram for data rate is 167 Mbits/s.  Figure 11. Power consumption dependence on data rates for data activity α= 1. Table 5 indicates the power consumption at different data rates for data activity α= 1. Figure 11 is power consumption versus data rates curves for Table 5. From this figure, From this figure, one finds that for a low data rate, DET llopis saves more power than that of DET chung . However, at a high data rate, the power consumption curve of DET chung starts to intersect the power consumption curve of DET llopis , which means that DET chung begins to save more power than that of DET llopis . Furthermore, for DET strollo , which is composed by 18 transistors always consumes less power than DET proposed under varying data rates, and the saving power percentage is between 4.8% and 12.6% for data activity α= 1.
In summary, from Tables 3-5 and Figures 9-11, one finds that DET pedram has the worst power consumption under all parameters. Generally, although the proposed DET proposed consumes a little more power than the circuit of the DET stroll for data activity α= 1, this situation does not affect its low power applications.

CONCLUSIONS
It has been observed that a significant amount of power consumption is generated by the clock line. This paper compares four previously published DETFFs together with our design for different metrics. As compared to four previously published DETFFs, our design outperforms in Electronic copy available at: https://ssrn.com/abstract=3278480 terms of power consumption and power-delay-product. Especially, the proposed flip-flop is superior in power reduction at different parameters, hence, it is well suited for low-power digital system applications.
One major advantage of the proposed DETFF is that it only requires a single clock signal, as contrasted with conventional DETFFs which require a clock chain to produce the correct timing that enables the circuit to function. In addition, the usage of differential data signals in the master portion of the proposed flip-flop circuit places very little capacitance on the clock line that will decrease the power consumption of the clock line. Furthermore, the proposed DETFF has the other advantages as following: (1) results in a latch sufficiently immune from glitches; (2) allows for the strong passage of data signals using single pass transistor of the same transistor type; (3) sufficiently reduces contention in the hold portion; (4) because of the reduction in the number of devices, the wiring necessary for the clock line of this latch is reduced. The proposed DETFF is simple in design, robust and reliable in operation, and efficient in operation.