Silicon-on-Insulator Technologies,--are We Converging on a Technique of Choice?

This paper attempts to present an unbiased review and evaluation of the dozen or more techniques under development to fabricate SOI structures. It includes an historical perspective, a review of the state-of-the-art, and an assessment of current SOI development programs in government and industry.


INTRODUCTION AND HISTORICAL PERSPECTIVE
Ten years ago, before we even had the term Silicon-On-Insulator (SOI), the technologies that fit into this category were heteroepitaxial Silicon-On-Sapphire (SOS) and the polysilicon substrate Dielectric Isolation (poly DI) technologyl. Both of these technologies are still with us today. Poly DI has been a workhorse in military strategic systems and SOS is finally making some inroads with military systems designers. SOS is unfortunately suffering from an image problem as a result of years of problems, even though it has made great strides in recent years, the most important of which is probably the development of a reliable materials quality screening technique2.
Even though these technologies fit the generic label SOI, what is generally meant by SOI is a single crystal silicon film on a silicon dioxide (or other insulating) layer on a single crystal silicon substrate. Beginning in the late 70s, work in this area has mushroomed. The IEEE SOS Workshop has become the SOS/SOI Workshop and virtually every microelectronics conference has an SOI session.
Even though many of the different SOI techniques are redicoveries of technologies several years or even decades older, the tremendous growth of interest in SOI as we know it today dates from the late 70s.
Many would argue differently as to the true beginnings of SOI, depending on their initial entry into the field, but we believe that it was laser processing that lit the spark and generated the environment in which many SOI technologies have flourished. It is ironic that laser recrystallization has been overshadowed by most of the other SOI techniques, although it may someday find a niche of its own.  circuits11'12 were made in it ( Figure 2). In fact, even though it had its own unique problems (grain boundaries and film thickness variations), it could compete with SOS in terms of material quality ( Figure  3).  SIMOX has made rapid advances. The initial goverment program produced a 4K RAM with excellent transient radiation hardness23. More recently a 16K RAM has been fabricated ( Figure 5a). In this technique, oxygen is implanted to very high doses (greater than 1 x 1018 cm-2). If the implant is done at elevated temperature (typically 500'C), sufficient surface crystallinity remains to serve as a seed for recrystallization of a surface layer (typically 200nm thick) during a subsequent high temperature anneal (1150-14000C). This anneal also redistributes the implanted oxygen to form a good quality buried silicon dioxide layer (typically 500nm thick). Nitrogen implantation has been performed as well24, to produce a buried silicon nitride layer, but with less success than with oxygen due to the small dose window. Too low a dose produces a poor quality insulating layer, while too high a dose results in nitrogen bubbles and delamination problems. Combining oxygen and nitrogen has shown some promise for increasing radiation hardness of the buried insulator. Anneal temperatures as high as within 50C of the melting temperature of silicon have been studied using special optical annealing furnaces25.
The main problem with SIMOX films at present is the high defect density. Until recently, defect densitites have been in the I x 108 cm-2 range. More recently researchers have claimed defect densities of 1 x 104 cm-2 with high temperature anneals. Contaminants introduced during implant are also being significantly reduced by careful machine design (silicon coating for anything in the beam path).
Major advances i4ion implanter design have been made, giving SIMOX the potential to compete as a practical production process. Following the initial modification of standard implanters to handle oxygen, very high current (100 ma) oxygen implanters have been designed and built ( Figure 6). The price is SIMOX wafers. Growing epi layers on SIMOX wafers is not trivial since one must be careful not to lose the thin seed surface film. Major advances in material quality were made as the temperature of the postimplantation anneal was increased. Defect densities are reduced and oxygen precipitates are dissolved.
high, however, and companies are slow to commit to the high capital and operating expenses.
Recrystallization of polysilicon films deposited on silicon dioxide layers has been accomplished in a variety of ways. Scanning laser or electron beams have been raster scanned over a wafer. Various techniques have been applied to change the shape of the scanned spot26 or various patterns have been fabricated in the wafer27 to control the thermal profile during recrystallization to improve material quality, principally by controlling the location of large angle grain boundaries. Alternatively, seeding through vias to the underlWin substrate was used to eliminate grain boundariest8,L9. The greatest success has been achieved with the line-source geometry of the scanning strip heaterl4 (Figure 7). Similar geometries can be produced with electron beams30 or high intensity lamps3l or simulated by rapidly oscillating beams6. Though a strong (100) texture is produced in capped layers even without seeding, large angle grain boundaries can be eliminated by seeding from vias to the underlying substrate. Until recently, it seemed that subboundaries (very low angle grain boundaries) were unavoidable. Though their impact on device performance and reliability is disputed, they still make people wary. Recent results with specially designed strip heaters (Figure 8) show subboundaries breaking up into discrete dislocations with densities comparable to SIMOX. Early problems with wafer warpage have also been solved. If these results hold up, such ZMR wafers will have advantages over SIMOX wafers. The quality of ZMR films does not degrade near the back interface, though some argue that the higher defect density near the back interface may reduce radiation induced back channel leakage. The  thickness of the insulating oxide layer is variable for ZMR SOI wafers and can be tailored to optimize performance. No epi is needed to produce film thicknesses typical for current CMOS processes and bipolar devices have been made directly in this material32.
ZMR apparatus is also inexpensive. Even in material with subboundaries fully functional IK SRAMs have been demonstrated3 (Figure 5b).
The other SOI technique that has demonstrated VLSI devices is FIPOS19t3 (Figure 9). In this technology, the field areas and the material below the device active areas are made porous by an electrochemical process. The pores then allow rapid oxidation giving a fully isolated device island. Drawbacks of this process are that the island size is limited and all islands must be approximately the same size, which limits device designers. Also, it is a wet chemical process which runs counter to the trend for VLSI processing. This technique is not being very vigorously pursued in this country. NTT in Japan, however has reported a 64K SRAM with this process34.
Another SOI technique that has been able to sustain considerable interest is Epitaxial Lateral Overgrowth (ELO)20 ( Figure 10). Periodic growth and etch cycles and/or special epi growth conditions are used to grow epi up through a via to the underlying substrate and out over an oxide layer while retarding the spontaneous nucleation of polysilicon on the oxide layer. Some successes have been achieved and understanding of the process continues to increase, but the technique is still limited by the necessity of pre-patterning and the limited lateral to vertical growth ratio thus far achieved. The potential advantages of this technique are the high material quality and the fact that epitaxy is a standard production process.
Related to this technique is the solid phase epitaxy of deposited polysilicon films from seed vias to the underlying substrate36. The Japanese continue to press hard in this area, though success has been very limited.
Another technique worthy of note is that of epitaxial insulators2l (Figure 11). In this ZZ technique, the insulating layer is grown epitaxially and is crystalline rather than amorphous as with the silicon dioxide layer in other SOI techniques. A silicon layer can then be epitaxially grown on the insulator. Examples are spinel, calcium fluoride, and boron phosphide. Many alternating layers of boron phosphide and silicon have been grown with the top silicon layer still being "device worthy" material37. It is an exciting concept, particularly for the potential of 3-D integration. Also, epitaxy is a viable commercial process. The materials problems associated with this technique, however, make SOS's problems seem minimal in comparison.
One last recently developed technique is also worthy of note22 ( Figure 12). The Bond and Etchback BOND & ETCHBACK Figure 12. SOI by oxide bonding of two wafers, followed by thinning of one of the wafers.
technique is a variant of the old poly DI technique except that a single crystal silicon substrate replaces the poly substrate as the "handle." Two wafers are joined together by an oxide bonding technique and then most of one of the wafers is removed as with the standard DI technique. This technique promises to solve the wafer warpage and "runout" problems of standard DI which prevent it from being used for VLSI. There are still problems with the bonding process and there is still question as to how much the silicon can be thinned with good uniformity. It may be an important technology as an improvement to standard DI for linear bipolar applications which require thick films.
It is worth emphasizing that different applications for SOI have different requirements. CMOS requires very thin films, now typically 0.3-0.5 pm. It may be advantageous to go to even thinner films (O.1im) as we go to submicron devices. Bipolar has different requirements for SOI. Digital bipolar requires 2-3pim films and linear bipolar requires 10-15jjm films. Material quality requirements are also different. Each of the SOI techniques has its own unique challenges in meeting these requirements.
Looking ahead to more advanced applications such as 3-dimensional or vertically integrated multi-layer structures, the current front running techniques such as SIMOX and ZMR may have difficulty, while others such as ELO or epitaxial insulators may have the edge. Stacked structures were first made in laser recrystallized material38.
Another potentially important application is mixed processing which combines SOI and bulk devices on the same chip. Here again, techniques such as ELO or even the original laser recrystallization may find their niche.
The government (particularly SDIO) has begun major development programs in SOI. The premier program, managed by DNA, focuses on SIMOX and seeks to demonstrate a 64K SRAM which is simultaneously very fast and very radiation hard. But other government programs are looking at most of the other SOI techniques and include bipolar as well as CMOS applications. SOI development programs in industry have similar variety.

CONCLUSION
We still haven't answered the question raised by the title of the paper. If we review what has been discussed about the advantages and disadvantages of the various techniques,--about the successes of the various techniques in terms of VLSI demonstration circuits,--about the variety of applications for SOI technology,--and about the variety of programs in government and industry,--the answer seems to be: no, we are not yet converging. But we claim that that is good. Considering the variety of applications, it would be unfortunate for various techniques to be abandoned prematurely. We believe that several techniques will eventually find their way into production rather than a single one.