A dynamic test method for high-resolution A/D converters

A dynamic test method is described for A/D converters having up to 16 bits of resolution. The technique exercises the test converter with stepped input changes, simulating the output of an S/H amplifier. Dynamic errors as low as 4 ppm can be measured within 4 ßs following a step change as large as 20 V.

Conditions 2)-4), however, place restrictions on these methods. Amplifiers, used either as the output stage of a D/A converter (a) or as a summing amplifier (c), suffer from settling time limitations for high resolution, and multiplexers (b) are limited by their ON resistance and settling time, particularly when driving significant loads. In the approach described here and illustrated in Fig. 1(d), conditions l)-3) are satisfied by superimposing a voltage pulse on a quasi-static level maintained at the output of an opera tional amplifier. The voltage pulse is created by switching on a programmable current through a relatively low-value (200-Ω) resistor in series with the amplifier's output to produce the voltage step, and switching the current off to return to the original voltage. To illustrate the concept, the step generator is shown as a simple combination of a current source and a resistor; the actual circuit is discussed later. Note that for the second transition in which the voltage returns to its original level, the settling time is largely determined by the speed with which the current can be switched off. Furthermore, after the U.S. Government work not protected by U.S. copyright current is switched off, the ON impedance of the current switch is no longer included in the input circuit, so that the second transition is immune to the ON resistance instability limitations inherent in example of Fig. 1(b). Fortunately, no voltage change is required of the amplifier during either transition but only the ability to quickly supply current to the resulting dy namic load. Thus the amplifier's settling time requirements are relaxed. This is easily verfied by monitoring the amplifier's output voltage during current switching. While the current pulse through the resistor is as large as 100 m A for a 20-V step, the amplifier must only supply a current change of 10 m A maximum, or V p /R m , where V p is the pulse voltage equivalent to VB -V A in the figure, and R m is the input resistance of the test converter (generally >2 kii).
To measure the dynamic response of a converter to these steps and thereby satisfy condition 4), the resulting step gen erator is applied in a manner suggested by the transitionlocking feedback loop employed in an NBS static test set for A/D converters [1], This circuit, shown in Fig. 2, uses discrete time (versus continuous) feedback to precisely locate and measure the static code transition levels. These are the input levels at which the digital output transitions between adjacent codes occur. Each transition is defined by the reference codeword applied to the digital comparator. In operation, the input voltage to the test converter oscillates with a triangular waveform about the transition level. The dither amplitude AV can be set arbitrarily low, e.g., a small fraction of a least sig nificant bit, by appropriate choice of integrator time constant, conversion rate, and integrator input voltage. Once locking has occurred, this transition voltage is easily measured using, for example, a high-resolution digital voltmeter, as shown.
The time intervals between data samples latched from the test converter represent periods of open-loop operation, and thus afford the opportunity of rapidly stepping the input voltage to different levels and back without disturbing the normal transition-locking feedback cycle. This dynamic ex ercise is accomplished by superimposing a voltage step on the integrator's output as described above and illustrated in Fig.  3. The step changes are made in between conversions with time allowed for settling. While the unit under test converts when the input is both at the pulse level as well as at the transition level, the feedback samples are latched only following con versions made at the transition level. If the superimposed conversion duration of test unit At time delay to allow for pulse to return to zero RC time constant of integrator. Any dynamic response error due to this superimposed step change will be manifested as a change in the code transition level maintained by the feedback loop. For example, the static level of the major transition (from binary code 01111. .. to 100000. . .) may shift as a result of thermal changes arising when the input is stepped periodically to full scale and back.
Fortunately, thermal changes in the integrator have no effect on the level maintained by the feedback loop, since this level is controlled entirely by the test converter. If the feedback and step voltages are summed with negligible interaction, then the transition voltage can be measured and its changes monitored quite simply at the integrator's output with the DVM. The dynamic measurement can, in other words, be transformed to a static one.
A manually operated test set has been built following these design principles. A 16-bit reference codeword is entered via a toggle register, and pulse voltage V p is set via potentiometer p. The ON and OFF durations of the pulse are entered from BCD switches whose settings M and TV control the number of conversions made, respectively, at the pulse level and at the transition level determined by the reference codeword. For N > 1, the converter is permitted two or more conversions to reach the final decision which controls the feedback loop. Al ternatively, delay At can be changed in smaller increments to determine an optimum recovery time.
The pulse current is driven from a follower amplifier having high-output drive capability, and is switched ON and OFF through resistor r via a junction FET having very low (<2-Ω) ON resistance and >30-V breakdown voltage. Since this ON resistance is in series with resistor r when the switch is on, it causes an uncertainty in the value of the pulse level given by Ronl(r + ^on) ^1 percent. The amplifier and switching transistor drive circuitry are all powered by a modular supply whose common terminal is connected to the integrator's out put, and is thus held at the transition level.
The settling time of the pulse (returning to the transition level) has been measured at the test converter's input using a modification of the "viewing circuit" described by Schoenwetter in [2]. The pulse was found to return to within 4 ppm (full-scale range) of the transition level in under 4 μ$ following a step change of 20 V. Additional observations at the inte grator's output during pulse switching revealed that the switching transients and level changes were insignificant, af fecting the average value by no more than 1 ppm.
With this test set, each of the four conditions initially stated can be met. Any of the 2 n levels in the defined range of the converter under test can be selected as the reference transition level, and any other level may be independently selected as the pulse level. While the pulse levels are not known to better than 1 percent, the transition levels are precisely defined, and any step can be accurately generated in terms of a return from a pulse level to a transition level. Since these steps do not ap preciably exercise any critical amplifiers, the settling time is kept short and the error band small. In addition, by excluding the switch resistance from the input circuit after the step is made, errors due to resistance instability in the equivalent input circuit are eliminated. Accordingly, converters having rela tively low input impedances can be tested without incurring proportionately greater errors due to switch resistance changes. Finally, with this method, dynamic errors are explicitly mea sured in terms of resulting deviations of the reference (codetransition) levels from their static values. These characteristics make the test set suitable for measuring the dynamic perfor mance of converters having resolution as high as 16 bits. At resolutions of greater than 12 bits, the test set can simulate an S/H amplifier having better dynamic response than any commercial products presently available. Furthermore, it seems possible that improvements in the switching circuit can lead to even shorter settling time. This, in addition to tradeoffs with accuracy, could extend the applicability to faster con verters of less resolution.