Medium power voltage multipliers with a large number of stages

Voltage multiplier techniques were extended at medium power levels to larger multiplication ratios. A series of DC-DC converters were built, with from 20 to 45 stages and with power levels up to 100 watts. Maximum output voltages were about 10,000 volts.

has proven that capacitor diode voltage multiplier (CDVM) DC-DC conversion with efficiencies up to 96 percent and at power levels up to 1 kW is possible. The multiplication factor, or ratio of DC output to DC input voltage in this previous work was about 8 or 10. This paper discusses the extension of this muitiplic.ation ratio for medium power multipliers, and explares large multiplica t lon ratios in terms of efficiency, weight, and operating characteristics. Multipliers with twenty to forty-five stages were examined both analytically and experimentally. Emphasis was placed on high efficiency and light weight. Some large multiplication ratio work has already been reported in the literature (6)(7)(8)(9)(10)(11). However, the converters were of low power and efficiency was not of primary concern.
EQUATIONS FOR LOAD VOLTAGE DROOP, OUTPUT RIPPLE, AND LOSSES The voltage multiplier used was of the type shown in figure 1. The multiplication ratio, at low power, is approximately equal to the number of stages. Each stage includes 2 capacitors and 2 diodes. Descriptions of the transistor drive and control circuits have previously been reported (1-4) and will not be tepeated here.
The output voltage was determined using techniques previously described by Harrigill  For large values of a, the average output voltage, within a few percent, can be written as: The first term, sV, is the no load vo:tage and may be considered analogous to the internal voltage of a generator. The second term, 21 Ls 3 /3fC, is the load voltage droop due to capacitor charging losses in the voltage multiplier This sclies voltage drop in the voltage multiplier gives rise to a power loss of 2s 7 1 /3fC. In addition to the DC output voltage V L , a r pple voltage V R with a frequency of f is superimposed on the output. This ripple voltage has a peak to peak value of i (s)(s + 1) _ VR L 2fC (3) For large multiplication ratios, the droop voltage, which is a function of s 3 , is much larger than the ripple voltage, which is a function of s2.
In addition to the capacitor charging loss, there are other losses. See reference (2) and tables I and II. Note that one loss is proportional to if, several are proportional to i L , and some are independent of i L . This suggeat.e that a maximum efficiency exists at some load current. In order to determine this point of maximum efficiency, an expression for efficiency in terms of i L was formulated and its dervfative with respect to load current set equal to zero. The efficiency q is equal to For a well designed voltage inutliplier, the input current is very nearly equal to the number of stages s times the load current.
where k i , k 2 and k3 are constants defined by: Where the symbols have been previously defined.
Tile Losses given by sVk l are independent of load current, the losses given by the k2 term (sVk2 1 L) are proportional to load current, and the k3 tern losses (2u 3 1j/3EC) are proportional to the square of the load current. The efficiency it can then be written in terns of k l , k2 , k3 and i t, as The trend in the efficiency versus load current curve, and the variation in efficiency with the number of stages s, is shown in the experimental results section.

OPTIMIZING THE NUMBER OF STAGES FOR A GIVEN OUTPUT VOLTAGE
It is desirable to select the minimum size The total Capacitance C T is 2s 2 (s + 1)(29/3 + 1/12)1L CT " One can now determine the optimum s by differentiation of Op with respect to s, and g utting the resultant expression equal to zero. From a strict mathematical standpoin` this is not possible, since a occurs in discrete, integral values. For this treatment, however, a will be considered cautionnos, and the nearest lntebral value taken, dCT do (s+1)^3s+12^+a +i2/+s(s+1^.7°i    Figure 3 shows the efficiency as a function of load with the number of muleiolier stages as a parameter. As expected, Lite efficiency decruaues wLth increasing number of stages, but still remains intlae middle and high 80 percent range for reasonable capacitor sizes, As can be seem from figure 3, 100