MOSFET optimization in deep submicron technology for charge amplifiers

The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the enhanced MOSFET model, when compared to the classical, produces a different resolution estimate and input MOSFET optimization result. The minimum channel length and the maximum allocated power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the Equivalent Noise Charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25 mum CMOS technology are reported


I. INTRODUCTION
1 PPLICATION Specific Integrated Circuits (ASICs) can be a valuable solution in front-end electronics for radiation sensors. Detection systems with high sensor pixellation can benefit from low power, low parasitics, high front-end channel density, and low cost per channel. In addition the ASICs are characterized by good radiation tolerance [1][2][3] and can integrate large amount of additional signal processing and functions in analog, mixed-signal and digital domains, offering further advantage in terms of power and real estate.
In a properly designed front-end the resolution is limited by the noise from the input transistor. Consequently a relevant phase of the design consists of optimizing the input MOSFET with respect to sensor, interconnects and the specific application. The choice of the polarity (n-or pchannel), size (length L and width W) and operating point (drain current density J d and drain-to-source voltage V ds ) are determinant in achieving the best performance. The optimization process relies on equations, models and parameters that can be strongly dependent on the technology. As deep submicron CMOS technologies are developed and characterized for digital design, the process of optimizing the input MOSFET can become very challenging. This contribution would like to provide the low-noise front-end designers with techniques to keep pace with the rapid evolution of CMOS technology.
After a review of the traditional optimization process, the impact of properly modeling the series noise and gate capacitance of the MOSFET is discussed. As an example, the commercial TSMC 0.25µm CMOS technology is characterized and investigated for the best achievable resolution.

II. THE ENC EQUATION
The resolution of a front-end can be measured in terms of Equivalent Noise Charge (ENC) [4][5][6][7]. The ENC corresponds to the charge that must be delivered to the front-end in order to achieve a signal to noise ratio equal to the unity.
In the following we will assume that the resolution of the front-end is dominated by the noise from the input MOS-FET, characterized by a gate length L, a gate width W and a drain current density J d =I d /W. We will also assume that the front-end implements a time invariant filter with overall pulse response to a charge Q equal to Q·h(t), and characterized by a maximum Q·h(t)| max . In Fig. 1 a schematic of the front-end for the evaluation of the ENC is shown. The parallel noise contribution 2 n i , characterized by a unilateral power spectral density S in , is typically related to the sensor leakage current, to its bias circuitry and to the charge amplifier feedback circuitry. In the following we will initially assume a white density S in =S p . Then, since this contribution is not related to the input MOSFET, this term will be neglected. The series noise contribution 2 n v , characterized by a unilateral power spectral density S vn , is dominated by noise processes in the input MOSFET. In the following we will initially assume a density S vn =A ƒ /ƒ+S w . The low frequency term, known as 1/ƒ noise, is strongly technology related. The white term is strongly related to the transconductance g m of the MOSFET. The input capacitance C in includes the sensor capacitance, the feedback capacitance and any parasitic connected to the input node and not dependent on the size (W,L) of the input MOSFET. The gate capacitance C g includes any term dependent on the size (W and/or L) of the input MOSFET.
The ENC can be expressed as follows: where τ is the time constant of the filter and H(s) is the where the time is normalized to an arbitrary time constant τ, and τ•H(sτ) is the Laplace transform of h(t/τ). Assuming as time constant the pulse peaking time τ p , calculated from 1% to the peak, and transforming the integrals variable, the (2) becomes: where the three ENC coefficients: depend only on the type of filter, and H(jx) is obtained replacing ω with x/τ p in H(jω). In Table 1 the coefficients for some commonly adopted time invariant filters are reported, along with the ratio between the pulse width τ w , calculated from 1% to 1% of the curve, and the peaking time τ p , calculated from 1% to the peak. The R-type filters have real poles only while the C-type filters, commonly adopted in commercial discrete shapers, have complex conjugate poles [8]. The order of the filters in Table 1 ranges from 2 nd to 7 th . It can be observed that, as the order increases, the ratio τ w /τ p decreases making the high order filters more suitable for high rate applications. Also, at equal order, the C-type filters offer a better τ w /τ p ratio than the R-type filters. Finally, the advantage of zero area for bipolar filters, which in absence of effective baseline stabilization at high rate can be relevant, is compensated by worse values in the series coefficients a w and a ƒ , especially for high orders.
Without loss of generality we will simplify our analysis by assuming a w =1, a ƒ =0.5, and a p =0.5, which are close to the typical values for a good time invariant unipolar shaper.
In the rest of the analysis the parallel noise contribution S p will be neglected, and the general expression for the ENC in (3) will be simplified as follows:

III. CONSTRAINTS, VARIABLES AND MODELS
The input MOSFET must be optimized for the minimum ENC. The ENC depends on some parameters not related to the input MOSFET, specifically the input capacitance C in , the peaking time τ p , and the maximum power P d_max available to the input MOSFET. Typically the input capacitance C in is set by the sensor and interconnects, the maximum power P d_max depends on system level constraints, and the peaking time τ p is set by the rate or ballistic deficit. In presence of non-negligible parallel noise contribution a further constraint on the peaking time may occur.
The typical optimization process consequently assumes C in , τ p , and P d_max as constraints. One further constraint derives from the use of a single supply V dd : where J d is the MOSFET drain current density. The (6) establishes a constraint on the J d ×W product. It follows that, once C in , τ p , and P d are defined, the ENC depends only on two variables: W (or J d ) and L. The optimization process will consequently return the two optimum values W opt (or J d_opt ) and L _opt that give the minimum ENC (ENC opt ).
In order to proceed with the optimization of the input MOSFET, the parameters C g , S w and A ƒ must be expressed as functions of W (or J d ) and L. In the following sections the modeling of these parameters will be discussed, starting from the solution that the CMOS designers frequently adopted in the past, before the advent of the deep submi-cron CMOS technologies.

IV. CLASSICAL (C) MODEL FOR C G , S W AND A ƒ
In the past the front-end designers frequently adopted the following models [9][10][11][12][13]: where C ox is the oxide capacitance, k is the Boltzmann constant, T is the absolute temperature, g m is the MOSFET transconductance dependent on J d and L, and K ƒ is the 1/ƒ noise coefficient. We will refer to this model as C-model. Introducing (7) in (5) it follows: where g mw (J d ,L) is the transconductance per unit of W.
The function g mw (J d ,L) can be easily extracted for specific values of L from a Spice simulation using the model and parameters available for the technology. The coefficient K ƒ can be extracted from a measurement of the input noise spectral density, it is assumed to be independent of L and it may differ for n-channels (K ƒn ) and p-channels (K ƒp ).
For the TSMC 0.25µm technology C ox ≈6.1fF/µm 2 , g mw (J d ,L) can be obtained from BSIM3v3.1 simulations (see Fig. 2) and, from measurements on samples with minimum L at 1kHz, it follows K ƒn ≈6×10 -24 J and K ƒp ≈0.3×10 -24 J. In Fig. 3 the optimum ENC for C in =1pF and τ p =1µs, calculated for n-and p-channels with different L as function of P d is shown. For minimum L the white and 1/ƒ components and the optimum W are also reported. It can be observed that in this case the p-channel offers a better resolution than the n-channel (lower K ƒ ) and this is generally true. It also indicates that the choice L opt =L min and P d_opt =P d_max offers better results in an amount that depends on the relative ratio between the white and 1/ƒ contributions.

V. ENHANCED (E) MODEL FOR S W
The model for S w in (7) provides a crude white noise estimation valid for long channel MOSFETs operating in strong inversion. In most cases the input MOSFET of a front-end operates in moderate to weak inversion, and a better estimate is needed. In addition, in deep submicron MOSFETs an excess noise factor above unity has been frequently reported.
An equation that better estimates the white noise in all regions of operation can be found in the literature [14][15][16]: where µ eff is the mobility, Q I is the total inversion charge, and α w is the excess noise factor. This equation can be approximated with [16]: where n≈(g mb +g m )/g m is the subthreshold slope coefficient ranging around 1.2-1.3 and γ(J d ,L) is a coefficient ranging between 1/2 and 2/3. The same authors of [16] proposed the following interpolation function: where u(J d ,L) is known as inversion coefficient and V t =kT/q. From the same authors is a simpler approximation for γ(J d ,L) [12]: A slower interpolation function is reported in [15], along with the companion model for the gate capacitance. A comparison to C g simulations and to noise measurements [2] suggests that (11), here adopted, might be more accurate. In For the TSMC 0.25µm technology n nch ≈1.2, n pch ≈1.3 and, from measurements, α w ≈1 whenever u<10 (weak and moderate inversion) and V ds -V ds_sat is small (V ds_sat is the drainsource saturation voltage). Good agreement with these results can be found in the literature [2,[18][19][20]. In Fig. 5 the optimum ENC from (13) for C in =1pF and τ p =1µs, calculated for n-and p-channels with minimum L as function of P d , is shown, compared to C-model results. The optimum W is also reported. It can be observed that the new model provides a better estimate especially at low power, where the white noise component dominates. A relatively small difference in terms of optimization (W opt ) can also be observed. The L opt =L min and P d_opt =P d_max still appears the best choice.

VI. ENHANCED (E) MODEL FOR C G
The gate capacitance C g in (5) includes any term dependent on the size (W,L) of the input MOSFET. A better estimate of C g should consider the gate-to-source and gate-todrain overlap components [15]. These extrinsic terms are proportional to the width W of the MOSFET and, in deep submicron technologies, are typically not negligible. In addition, the intrinsic component of C g in saturation is a fraction ≈2/3 of C ox WL [15]. An equation that improves the estimate of C g , here referred as Ci-model, is: where C ov is the overlap capacitance density, equal for drain and source. Introducing (14) in (13) it follows:  In Fig. 6 the optimum ENC from (15) for C in =1pF and τ p =1µs, calculated for n-and p-channels with minimum L as function of P d , is shown. When compared to Figs. 3 and 5 it can be observed that the choice L opt =L min does not apply anymore. Both n-channel and p-channel can offer better resolution for L higher than L min . This conclusion is valid whenever 1/ƒ noise dominates, and can be understood by rewriting (15) for this case: By calculating the differential of (15) with respect to W, U.S. Government work not protected by U.S. copyright the optimum width for the minimum ENC can be calculated for each L: (17) Capacitive matching applies (C g =C in ) and, by superposition, the ENC opt can be written: The plot in Fig. 7, derived from (18) for n-channel MOSFETs, illustrates the impact of L on the optimum ENC for the case of dominant 1/ƒ noise. Intuitively, as L increases the 1/ƒ noise contribution decreases more rapidly than the increase in gate capacitance.  The Ci-model (14) for C g doesn't take into account the dependence of the intrinsic gate capacitance on the drain current density J d . This dependence in deep submicron technologies can be not negligible, especially in the transition from weak, thorough moderate, to strong inversion. An enhanced (E) model for C g can be written as: where C gw (J d ,L) is the gate capacitance density and includes the bias dependence, intrinsic and extrinsic components.
As for g mw (J d ,L) the function C gw (J d ,L) can be extracted for specific values of L from a Spice simulation using the model and parameters available for the technology. For the TSMC 0.25µm C gw (J d ,L) can be obtained from BSIM3v3.1 simulations as shown in Fig. 8. The results for C-and Cimodels for the n-channel at minimum L are reported for comparison. It is worth noting that the cutoff frequency of the MOSFET, given by g m /(2πC g ), remains an increasing function of J d and, in the regions of interest, typically exceeds the tens of MHz.   Introducing the (19) in (13) it follows: (20) In Fig. 9 the optimum ENC from (20) for C in =1pF and τ p =1µs, calculated for n-and p-channels with different L as function of P d , is shown. For two cases the 1/ƒ component and the optimum W are also reported. It can be observed again that the choice L opt =L min does not apply. In addition, for n-channel MOSFETs, the choice P d_opt =P d_max does not apply, since they can offer better resolution at P d lower than the maximum available.   Fig. 9. Simulated ENC opt vs P d for n-and p-channels with different L in TSMC 0.25µm adopting the E-model for S w and C g . This conclusion is valid whenever 1/ƒ noise dominates, and can be understood by rewriting (20) for this case: By taking into account (6) and calculating the differential of (21) with respect to W, the optimum width for the minimum ENC can be calculated for each L: Capacitive matching does not apply except for the regions where ∂C gw /∂J d =0 and, by superposition, the ENC opt turns out to be: The plot in Fig. 10, derived from (23) for n-channel with minimum L and C in =1pF, illustrates the impact of P d on the optimum ENC for cases of dominant 1/ƒ noise. The ratio C g_opt /C in is also reported. Intuitively, as P d increases the gate capacitance increases while the 1/ƒ noise contribution does not change.

VII. ENHANCED (E) MODEL FOR LOW-FREQUENCY NOISE
In Fig. 11 the typical equivalent input noise spectral densities measured on n-and p-channels in TSMC 0.25µm with different L are shown, and are compared to the 1/ƒ slope. Two relevant details should be observed. The first concerns the slope, which differs from 1/ƒ, being in this case higher for p-channels and lower for n-channels. The second concerns the ratio between spectra, which is higher (≈2.4 for L=0.24µm vs L=0.48µm) compared to the square root of the ratio between L (≈1.4 for L=0.24µm vs L=0.48µm). A similar trend for short channels in deep submicron technologies was reported by other authors [2,[22][23][24][25].
In Fig. 12 the typical spectra for n-and p-channels with L=0.24µm at different drain current densities J d are shown. The dependence of the low-frequency component on the bias point appears negligible. This result seems in agreement with others in the literature for MOSFETs operating from weak inversion up to the border between moderate and strong inversion [3,[26][27][28][29], which is the region of inter-est for our applications. Some authors have reported an increase moving towards very strong inversion [28][29][30].
where K ƒ (L) now depends on L, and the slope depends on the coefficient α ƒ .
The non-1/ƒ slope requires a review of the low-frequency component ENC LF of the ENC. The second term of (2) now becomes: and ( where the ENC coefficient a ƒ (α ƒ ) is given by: Concerning the two other coefficients in (4) it is worth noting that a w =a ƒ (0) and a p =a ƒ (2). In Table 2 the ratio ρ ƒ =a ƒ (α ƒ )/ a ƒ (1) is calculated for the filters of Table 1.
For the TSMC 0.25µm technology typical values for K ƒ and α ƒ are reported in Table 3. As in previous cases we will simplify our analysis by assuming ρ ƒ =1.05 for n-channels and ρ ƒ =0.95 for p-channels, values close to the typical for a good time invariant unipolar shaper. As consequence of the non-1/ƒ slope, a front-end optimized for a peaking time τ p_opt will show in the ENC a lowfrequency noise component dependent on τ p , as shown in Fig. 13 for the case C in =1pF, P d =200µW, τ p_opt =1µs.  By applying (28) to the TSMC 0.25µm CMOS it is possible to estimate the ENC achievable with this technology. The results below will give a general idea of what to expect. An exhaustive analysis is beyond the scope of this work.  In Figs. 14(a) and 14(b) the ENC opt and W opt for C in =1pF and τ p =1µs, calculated using the E-model for n-and pchannels with different L as functions of P d are shown. For comparison the two minimum L cases with the C-model are reported. The difference between E-and C-model in the estimate of the ENC opt for the n-channels is relevant, while for the p-channel may appear small. On the other hand the difference in terms of optimization (W opt ) is in both cases relevant.  (b) Fig. 15. Simulated ENC opt and P d_opt vs (a) τ p and (b) C in for n-and pchannels with different L in TSMC 0.24µm adopting the E-model. In Figs. 15(a) and 15(b) the ENC opt and P d_opt for C in =1pF vs τ p and for τ p =1µs vs C in , calculated using the E-model for n-and p-channels with different L, are shown, assuming a power budget limit of P d_max =1mW. In the case of Fig. 15(a) the reduction in P d_opt can be observed for higher values of τ p . In the case of Fig. 15(b) the reduction in P d_opt can be observed for smaller values of C in . In both cases this is consequence of the dependence of the gate capacitance on the drain current density, which pushes the input MOSFET towards the weak inversion.
In Figs. 16(a) and 16(b) we report some experimental results from two front-end ASICs recently developed in TSMC 0.25µm CMOS. In Fig. 16(a) The ENC vs C in from a prototype for a Time Projection Chamber [31] is shown. The ASIC implements 32 front-end channels with n-MOS inputs, 16 with L=0.24µm and 16 with L=0.36µm. The gate capacitance was, in both cases, on the order of 1.4pF. We observed a ≈40% difference in ENC slope, a result that appears in line with the discussion here presented. In Fig.  16(b) the ENC vs τ p from a prototype for a Coplanar Grid Sensor [32] is shown. The ASIC implements an n-MOS input with L=0.36µm. The gate and input capacitances were on the order of 12pF and 60pF respectively. A lowfrequency noise component proportional to ≈τ p -0. 15 , in agreement with α ƒ ≈0.85, can be observed.

IX. CONCLUSIONS
The optimization of the input MOSFET for charge amplifiers in deep submicron technology requires a proper modeling of the series noise and gate capacitance, and a review of the ENC equation. The enhanced modeling and associated ENC equation presented here allow a better ENC estimate and a more accurate optimization. The analysis shows that the traditional choice of selecting the minimum channel length and the maximum of the available power do not always offer the best resolution. Also, for a defined front-end, the low-frequency noise contribution to the ENC may de-pend on the time constant of the filter. The results here reported are based on the commercial TSMC 0.25µm CMOS, but can be easily extended to other deep submicron technologies.