Soft error immune GaAs circuit technologies

Cosmic radiation induced soft errors present a major difficulty for space applications that utilize digital GaAs circuits and systems. Techniques to reduce soft error sensitivity by 5 orders of magnitude or more, to sufficient levels for safe implemention of GaAs ICs in space applications are presented. These results show that the need for redundancy and error correction is eliminated. Space systems will benefit by reduced power and area requirements, plus a substantial improvement in system performance over present radiation hardened silicon-based technologies.


I. INTRODUCTION
Non-permament errors induced in space-based microelectronic circuits by cosmic particles are referred to as soft errors or single event upset (SEU) [ 11. Soft errors are localized non-permanent effects unlike total ionizing dose effects which produce permanent failures by threshold voltage shifts or transconductance degradation. Single ionizing particles known as heavy ions (cosmic rays), or highly energetic particles such as Van Allen Belt protons colliding with lattice atoms can create sufficient ionized charge in an "off' transistor to switch the transistor to an "on" state. This unintentional switching of the transistor can develop erroneous logic states in a bistable circuit or unexpected pulses in a clocked circuit. Soft error effects may range from interrupting noncritical operations, to rendering satelite systems useless until restarted [2].
Techniques to mitigate the sensitivity of soft error effects such as logic gate redundancy at the circuit level, or majority voting and error correctioddetection at the system level can compromise system performance. Shielding can incur a serious weight conStraint while only limiting the lowest energy particles. Circuit and system level solutions normally include tradeoffs in functionality, power and weight. Device level techniques that do not require these tradeoffs are the most preferable, although they are the most difficult to implement in an IC fabrication process.
To provide a measure of soft error sensitivity, Figure 1 portrays the soft error rate for various technologies against each power-speed product. The preferable technology for space applications would be one that provides the lowest speed-power product and the lowest soft error rate (the lower left of Figure 1 Most space systems require soft error rates below 10s errorshit-day. A processor or ASIC which includes lo5 gates may experence 100 errors a day in MESFET Direct Coupled FET Logic (DCFL), or 1 error a day in a C-HFET family. At clock frequencies of 400 MHz, soft error rates may increase by a factor of three [4]. As operating frequencies increase and power-speed products reduce, sensitivity to soft errors increases.
SEU sensitivity is related to several factors: energy transfer in the semiconductor, drift and diffusion of free carriers, transistor dimensions, noise margins, logic swings, capacitance, and the operating frequency of the circuit. In GaAs FET technologies, a progression of improved gate barriers from a MESFET, to EJFET and HFET has allowed improved logic swings and noise margins which in hand reduced soft error rates, as shown in Figure 1. Figure 2 gives a device and circuit view of an error created by a passage of a cosmic particle through the transistor structure.

CIRCUIT AND DEVICE SIMULATION
To understand the mechanics of an upset, combined device and circuit simulations were performed. These simulations analyzed DCFL utilizing implanted GaAs MESFETs. Several physical mechanisms internal to the FET contribute 'to the terminal photocurrents such as photoconductivity, drift, diffusion, bipolar action, and back channel modulation [5]. Both the circuit components and device parameters interact, however the most critical of these effects in the GaAs FET is the existence of excess charge below the FET channel, specifically hole concentrations. In contrast to SO1 which utilizes the Si02 insulator as a potential barrier, it was recognized that if materials with very high recombination rates were utilized as a buffer, the reduction in soft error rates may be more substantial than using an insulator [7]. A practical candidate was to use low temperature grown GaAs (LT GaAs) buffer layers beneath the transistor. This was accomplished by growing Molecular Beam Epitaxy (MBE) GaA!; on a bulk GaAs wafer, then lowering the growth temperaiture to grow non-stoichiometric arsenic-rich GaAs. The low temperature growth is followed by a deposition of high quality epitaxial GaAs above the LT GaAs and an annealing step I @ ] . The purpose of the arsenicrich material is to introduce complexes that trap and recombine excess electrons imd holes. The effective carrier lifetime of the LT GaAs material is approximately 1-10 ps, several orders of magnitude lower than the bulk GaAs characteritic lifetime of 1 ns [9]. Ionized charge in the buffer layer recombines 2 to 3 orders of magnitude greater than in the substrate or in the upper epitaxal layer. A transmission electron microscopy photograph in Figure 3 shows an cross section of a heterostructure FET on a LT GaAs buffer. The lower re,gion in the figure is where As precipitates are observed, a precursor to high recombination.
To model the effectiveness of utilizing LT GaAs buffers, combined devicekircuit simulations were performed to understand both the effects of introducing a LT GaAs buffer below the transistor structure, and effects on charge collected on the circuit nodes. The software utilized was Silvaco's ATLASTM and MIXEDMODETM device and circuit simulators.  One technique that has shown considerable advantages to reducing soft error rates in silicon technologies is silicon-In addition to the computer modeling, actual picosecond time-resolved measurements were obtained inside a GaAs circuit to confrm modeling predictions on the standard technology. A time-resolved photoconductive probe was utilized to measure laser-induced voltage transients internal to an integrated circuit to simulate a soft error event. Figure  2 provides the schematic for both the device and circuit modeling, and Figure 4 shows a comparison between simulation and measurement of a voltage transient at the output of a DCFL inverter. The initial fall is dependant on photoconductive and drift currents, whereas the eventual return to logic high is influenced by hole lifetimes and circuit time constants. Figure 5 illustrates the generic structure of the FET incorporating the LT GaAs buffer layer. Two MBE-based digital GaAs FBT processes, the Motorola CGaAsTM [lo] and the Honeywell C-T [ l l ] have implemented LT GaAs buffers, and have been measured for soft error effects. Additionally efforts to implement LT GaAs buffer layers into the implanted Vitesse HGaAsIIITM MESFET process are being pursued [ 121. For the MBE FET processes, the epitaxial wafer with the LT GaAs buffer is virtually identical to the original wafer. Because the LT GaAs buffer is implemented during the wafer growth, the IC fabrication process, layout masks, and circuit designs are unaltered. By substituting the initial wafer, a GaAs commerical process could be hardened for space radiation effects.
-. Figure 6 Hole concentration at 8 ps after an event for the conventional (left) and LT GaAs buffer structure (right). Figure 6 shows the hole concentration of both types of GaAs MESFETs biased in an inverter. Notice that much lower hole concentrations exist in the LT GaAs structure after the initial event. The LT GaAs buffer essentially acts as a sink to absorb excess carriers.

IV. RESULTS
Several experiments have shown excellent reductions in soft error vulnerability for both the Motorola and Honeywell GaAs FET technologies [10,11]. These experiments are from the first iteration of implementing LT GaAs buffers in these technologies. Efforts are continuing in all of the mentioned processes and further improvements are expected. Heavy ion experiments on the Motorola technology has shown three to five orders lower soft error rates for digital GaAs logic operating at 200 to 300 MHz. These levels are equivalent to observing one error for lo6 bits every 4 months to 27 years respectively in geosynchrounous orbit. The results on a Honeywell, C-HFET shift register operating at 68 MHz showed complete immunity to heavy ions [ 113. These soft error rates are more than sufficient to meet the most stringent requirements for space based applications. It is interesting to note that these results are taken during dynamic operation of the GaAs test circuits, where soft error sensitivity is more pronounced than with static tests on memories or latches [4]. Table 1 lists present data available on digital GaAs circuits tested with LT GaAs buffers. Threshold Linear Energy Transfer (LET) in MeV/mg/cm2 is the induced charge track density to initiate upset. The sensitive cross section is the sensitive area per bit and the soft error rate (SER) is estimated for geosynchrous orbits. We expect the improvements for the DCIX MESFET technology will not be as large as observed for the cases in Table 1, but SER improvements may be as much as 3 orders of magnitude.  ?.rr

Improvement Factor
Utilizing Low Temperature grown GaAs buffer layers in digital GaAs FET processes provides many advantages to the circuit and system designer requiring radiation hardened ICs for space applications: 1. No redesign of masks or circuits are required. Only a wafer substitution is needed.
2. Digital GaAs processes can now provide Commercial-Off-The-Shelf (COTS) ICs with excellent radiation hardness for new commercial and military space systems. No increased costs are incurred for developing a specifically designed rad-hard integrated circuit processes.
Utilizing rad-hard GaAs processers and Application Specific Integrated Circuits (ASICs) in space applications can provide an order of magnitude increase in data rates over present radiation hardened silicon technologies.
By eliminating the need for error correction or redundancy to mitigate soft errors, GaAs-based space systems can can obtain savings from weight, volume and power reductions.