Low temperature (LT) grown GaAs buffer layers for III-V semiconductor processes

Low Temperature Grown (LTG) GaAs buffers have been shown to eliminate backgating, reduce subthreshold leakage, provide ultrashort carrier lifetimes and radiation hardness. However, undoped LTG buffers have shown poor reliability, poor RF performance and inconsistent lot-to-lot properties. Recent p-doped LT GaAs buffers promise thermally stable material to withstand changes during annealing steps, plus improved performance over undoped LT GaAs buffers.


I. Introduction
Over 10 years ago, it was discovered by researchers at MIT that GaAs grown with As overpressure at low temperatures provided higher resistivity and shorter carrier lifetimes than observed in normally grown epitaxial or bulk GaAs [l]. Implementing LT GaAs buffer layers below FET structures eliminated backgating, and improved output resistance. This material is also utilized for ultrafast optical switches. Later it was recognized that LT GaAs buffers could provide soft error immunity for GaAs ICs [2] The low temperature Molecular Beam Epitaxy (MBE) growth is used to provide a non-stoichiometric material with approximately 1-2% excess As in the GaAs crystal. The defects present in this low temperature grown GaAs are As antisites (AsGJ and Ga vacancies (V,J To achieve the highest resistivities, the growth temperature is required to be in a tight window between 2OOOC and 220°C. However, there are several problems due to this growth requirement: 1) thermocouples in production MBE systems have difficulty accurately measuring this temperature at the wafer surface, 2) below 200°C the material becomes noncrystalline, 3) above 220°C the resistivity reduces dramatically, and 4) heat from the ion sources can alter the wafer temperature. These problems make it difficult for production MBE vendors to consistently provide reproducible material.
Problems also arise in utilizing LTG material for buffers under GaAs FETS. Once annealed, (intentionally or by continuing epitaxial growth or by implantation annealing) the properties of the undoped LTG material change. These anneals allow excess As to precipitate into clusters which reduces the strain in the non-stoichiometric layer. The As movement is assisted by VG, present in the LTG. The resulting material has high resistivity due to the As, which act as deep electron traps. The As, " is ionized due to the ptype VG, and thus provides an excellent electron trap in the sub-picosecond regime. Recombination mainly occurs between the V,, hole trap and AsGa and is on the order of several hundred picoseconds. The concentrations of these traps are on the order of 10'9/cm3 to lOZ0/cm3.
Other problems associated with defect movement are As or V, migrating outside of the intended buffer region. These point defects degrade performance by reducing activation of Si implants. Most techniques to alleviate this problem either utilize a difision barrier, such as AlGaAs or AlAs or place the buffer sufficiently below the FET. Both techniques can compromise performance. Wide bandgap diffusion barriers can influence the back-channel properties and may provide difficulty when using the same diffhion barrier under both N and P channel FETs. Placing the barrier far below the FET does not effectively reduce backgating.
For digital circuits, Honeywell and Motorola has used the undoped LTG buffers in their Complementary Heterojunction FET (CHFET) and Complementary GaAs (CGaAsTM) processes respectively. The two major reasons to use the LTG buffers were to reduce backgating and to improve the soft error immunity for space applications [2,3]. However, the use of undoped LT GaAs buffers in some of these processes can cause reduction in transconductance if the buffer is in the vicinity of the channel. Fig. 1 shows that the LT buffer can be inserted into the Honeywell CHFET process without degrading I-V characteristics of either the N-channel or P-channel FETs. The CHFET process utilizes the LT buffer with no change to the circuit design, layout, or wafer fabrication process.
For RF devices, LT GaAs buffers have shown poor performance. Even though DC output conductance ' and backgating voltages have been shown to improve dramatically, the noise performance for devices on LT GaAs buffer has been consistently poor. Diffusion of V , , fkom the LT buffer into the channel and or DX centers in the AlGaAs difision barriers have been suggested to account for the poor performance [4,5]. Gate W/L= 10/0.6um. LT buffer is located 3000 A beneath the AIGaAs/LnGaAs/GaAs heterostructure.

P-doped LT GaAs Buffers
In 1997, P. Specht et. al. at UCB studied the use of a pdopant Beryllium (Be) in the growth of LTG GaAs [6]. Their initial results showed thermally stable buffers, but also improved electron trapping due to the AsG,, becoming doubly ionized. However, one important aspect of this work for manufacturing was that the MBE LT GaAs buffer could be grown between 275°C to 350"C, a much more suitable environment for MBE growth. The implementation of the Be dopant provided several improvements to the LT GaAs buffer. These were: 1) The Be occupied the V, site, thus reducing vacancies in the material, 2) The Be concentration became the dominate mechanism to control resistivity other than growth temperature, 3) The BeGa acceptors stabilized the point defects (i.e. AS,,) by frrst mechanical compensation due to the smaller Be atom and second electrically by the double ionization of the As, . Fig. 2 illustrates the differences between undoped LT GaAs and Be-doped LT GaAs.
Controlling the p-dopant in the LT GaAs allows the flexibility of adjusting resisitivity, carrier lifetime, defect stability, or breakdown field. Recent results from UCB have shown breakdown fields of 5 x lo5 V/cm and resistivities greater than lo9 ohm-cm can be achieved [7].
After UCB's initial results, UCB and Quantum Epitaxial Devices (QED) grew epitaxial GaAs and GaAs HFET structures on Be-doped LT GaAs buffers for implanting studies at the Naval Research Laboratory (NRL) and device fabrication at Motorola respectively. The initial expectation was that the Be would diffuse out of the LTG buffer layer, similar to the problem known in Be-doped HBT bases [8]. The results showed very good stability in the 5000A Bedoped LT GaAs layer. Fig. 3 is an "as grown" sample, and Fig. 4 is after a 850°C, 10 second RTA anneal. A furnace annealed 700°C for 60 minutes sample (not shown) showed stable Be, but some Si moved out of the n-type substrate.  Implementing LTG buffers in an implanted E D MESFET process has also been pursued. Two issues exist:

Fluence
Fluence 6 x 1Oi2/cm2 4 x l0l2 lcm2 defects has shifted the threshold. Both LTG samples 13 1 l a and 1312a were identical but different lots. This shows the problems of wafer-to-wafer uniformity.
As just shown, a challenging problem is to show good activation for ohmic or channel implants in epitaxial material above an LT GaAs buffer. Si implant studies ( Table 1) at NRL have shown that activation in a 3000a GaAs epitaxial layer above a 5000A Be-doped LT GaAs layers is slightly improved over bulk and is equivalent to conventional epi material [9]. This was the first time activation has shown to improve with LTG buffers.

Actived in
Wafers grown at QED with Be-doped LTG buffers were fabricated in Motorola's CGaAsTM process in parallel with undoped LTG buffers. The Be concentrations were 8~l O '~/ c m~ and IO''/cm3 and buffer growth temperatures of 320°C and 295°C were used. Various ohmic implants were used. All of the N-channel Be-doped LT GaAs samples outperformed the undoped samples. The N-channel transconductance exceeded the undoped LTG buffer devices by 11% to 5 1%. P-channel device transconductance ranged from 14% improvement to a 38% reduction. N-channel subthreshold was one to two orders of magnitude lower than the undoped LTG devices [lo]. Analysis of the QED wafers by UCB showed these first Be LTG buffers were slightly ptype increasing the P device leakage. Fig. 6 and Fig. 7 show device I-Vs.   Fig. 7 shows an I-V characteristic of a 1x10 pm N-"ET fabricated on a Be-doped (32OoC, 8~1 0 '~ Be) LTG buffer. Vgs in steps of 50mV, V, maximum is 0.8 volts.

Conclusions
The use of p-dopants in LTG buffers open a new approach to use precise control of point defects to control electrical properties and to provide thermal stability. The Be-doped LT GaAs buffer can not only provide high resistivity equivalent to undoped LTG buffers, but also provide more efficient trapping and recombination properties. The LT GaAs buffer layer, unlike insulators which block conduction (and introduce interface states), acts as a sink to absorb scattered hot carriers. Backgating effects hamper GaAs FETs (and SO1 devices) however, the use of LTG buffers can provide a constant Fermi level without contacting conductive underlayers or body ties. Since the Be-doped LTG has reduced VGa's, and no difision barrier exists to introduce DX centers it remains to be seen if a RF device on a Be-doped LTG buffer can show improved performance.
Thus, the ability to manufacture thermally stable LT GaAs buffer layers can: improve performance: higher G, than previous LT buffers, eliminate backgating, lower subthreshold leakage, provide simple implementationwafer substitution, be applicable to other material systems -InAMs/lnGaAs P-HEMT and HBT devices, increase soft error immunityalpha particle sensitive and space applications.