An investigation into a low insulation resistance failure of multilayer ceramic capacitors

An investigation was conducted into failure of a multilayer ceramic capacitor (MLCC) mounted on a printed circuit board assembly. In field use a particular assembled 0.1μF MLCC (0402) was exhibiting low insulation resistance. Failure analysis was conducted to evaluate materials, manufacturing and assembly processes and the testing environment to identify a set of possible failure sites and mechanisms associated with the assembled MLCC that would produce the reduced insulation resistance. A physical analysis plan was developed and executed to investigate identified sites within the failed MLCC assembly. The analysis techniques included X-ray inspection, cross-sectioning with in-situ direct current (DC) resistance monitoring, optical microscopy, environmental scanning electron microscopy (E-SEM) and energy dispersive spectroscopy (EDS). The failure was isolated to a tin-rich material found under the MLCC causing the loss of insulation resistance between the end terminations of the MLCC. Some possible causes for the presence of the metallic material under the capacitor are reviewed and recommended corrective actions are provided.


Introduction
Multilayer ceramic capacitors (MLCC) are widely used in electronic assemblies for telecommunication, data processing, automotive and many other applications. Capacitors frequently outnumber all other components in these assemblies [1]. For example, approximately 90% of the components in a cell phone are passive components and approximately 60% of the passive components are capacitors [2]. The market for capacitors is currently more than $5 billion per year, with over a 1 trillion ceramic capacitors sold each year [3].
An MLCC, a rectangular component with solderable conductive terminations, is made of thin layers of a specially formulated ceramic dielectric sandwiched between metal electrodes which are alternately connected to the opposite edges of the structure. The laminated structure is subsequently sintered at high temperature to fabricate the MLCC which provides the required values of capacitance.

Experimental Approach and Results
CALCE received a request to investigate the cause of failure on an electronic assembly. Failure site isolation revealed low resistance across a surface mount 0402 MLCC that was mounted on the printed circuit board assembly (PCBA). The capacitor was a typical MLCC with barium titanate dielectric and nickel electrodes. The end terminations were made of copper with nickel plating. Elemental analysis indicated that the solder used on the board contained tin (96%) and silver (4%). A physical analysis plan was developed and executed to identify and localize the failure site. The analysis techniques included optical microscopy, environmental scanning electron microscopy (E-SEM), energy dispersive spectroscopy (EDS) analysis, X-ray analysis, and cross-sectioning with in-situ direct current (DC) resistance monitoring.

I: Optical & E-SEM Inspection-
Optical & E-SEM inspection of the failed MLCC and the surrounding area was performed to investigate the low resistance path. Due to the small size (2 inch by 1 inch) of the printed circuit assembly, non-destructive E-SEM inspection was possible. The E-SEM micrograph in Figure 1 shows the MLCC in the white oval and the area surrounding it. Figure 2 shows another view of the failed 0402 MLCC and the surrounding area. E-SEM inspection revealed the presence of a thin layer under the capacitor body which was an anomaly. Figure 3 and Figure 4 show magnified views of the material under the MLCC. Since the thin layer was trapped underneath the MLCC, (EDS) analysis was not possible. A crystal oscillator was also observed close to the failed MLCC, mounted on the board with its side soldered to a relatively large solder pad of area 0.5 inch by 0.4 inch.
II: X-Ray Inspection-X-ray inspection was performed after the optical and E-SEM inspection to look for internal anomalies. X-ray inspection of the PCBA and the MLCC did not reveal anything abnormal. Due to the small size of the MLCC, the orientation of the electrodes inside the capacitor could not be determined from the X-ray images.
III: Cross-Sectioning with in-situ Resistance Monitoring-A technique that enabled in-situ DC resistance monitoring while performing the cross-section through the electrodes of the MLCC capacitor was developed. The objective of this in-situ monitoring of the resistance was to stop the cross-sectioning as soon as the resistance increased in order to analyze the failure site.
Initial measurement of the insulation resistance across the MLCC was measured as 18 Ohms. The value of resistance for a non-compromised MLCC is typically hundreds of mega Ohms or more. The area containing the capacitor on the PCBA was sectioned and the resistance was measured again across the MLCC end terminations and was confirmed as 18 Ohms. The MLCC was not desoldered from the printed circuit board because application of heat could have destroyed or compromised the cause of failure.
For in-situ monitoring of insulation resistance during cross-sectioning, 0.01 inch diameter copper wires were attached to the end terminations of the MLCC using a silver conductive epoxy. The other end of the wires were connected to an Agilent 34405A benchtop multimeter. Solder was not used to attach the copper wires to the end terminations to avoid exposing the MLCC and its solder joints to heat from the soldering iron tip.
Since X-ray analysis was unable to reveal the orientation of plates inside the MLCC, it was decided to cross-section the MLCC from the top longitudinal edge towards the diagonally opposite lower longitudinal edge as shown in Figure 5. The PCBA area containing the MLCC was mounted in a two part epoxy to preserve the defect. A special fixture was designed to hold the sectioned PCBA area containing the MLCC. The cross-sectioning setup consisted of an automated grinder/polisher, the multimeter and associated cables, shown in Figure 6. A Buehler MPC 2000 precision polisher was used for the cross-sectioning. The MLCC was cross-sectioned at low rotational speed (<30 rpm) starting with 15 micron particle size diamond lapping film discs and then progressively moving to lower particle size discs. During the grinding/polishing process of the MLCC, the insulation resistance was continuously monitored. Figure 7 shows an intermediate cross-sectional plane of the MLCC. The crosssectioning was stopped as soon as the insulation resistance increased to a few mega Ohms. IV: E-SEM/EDS Analysis after Cross-Sectioning-E-SEM/EDS analysis was conducted after the crosssectioning to investigate the failure site, which could potentially be either inside or outside the MLCC body, in order to determine the cause of failure. Figure 8 shows the E-SEM image after cross-sectioning. No anomalies were found between the electrodes or elsewhere inside the MLCC body. Some foreign material was observed under the capacitor, in the same relative region as was observed during the previously reported E-SEM inspection, shown in Figure 3 & Figure 4. Figure 9 shows a magnified view of the unknown material.  Table 1. EDS mapping was performed under the MLCC as shown in Figure  10. In the right image the purple/light colored region under the MLCC shows tin. The tin-rich thin layer under the capacitor extended from one termination to the other, providing a low resistance conduction path. The tin-rich layer was primarily concentrated close to the center of the capacitor but extended from one termination to the other. This would explain the perceived drop in insulation resistance across the MLCC.  Oscillator-Since the material under the failed MLCC was consistent with stray solder material, the region surrounding the MLCC was analyzed to identify any design features that could be related to this observation. The crystal oscillator with the large solder pad which was observed during the initial optical inspection was cross-sectioned to expose the solder under it. Figure 11 shows an E-SEM micrograph of the solder joint under the crystal oscillator. EDS analysis results of the solder is shown in Table 2.

Discussion
A low resistance path across an MLCC mounted on a printed circuit board assembly (PCBA) was investigated. The low resistance path was found under the MLCC. Some mechanisms that can cause a low resistance path under an MLCC are: dendrites due to electrochemical migration, inadequate cleaning of the stencil between uses, and solder paste dislodged from the stencil after the solder has been applied while the stencil is being removed. Electrochemical migration is a failure mechanism characterized by the growth of conductive metal filaments, or dendrites, on a PCBA through an electrolyte solution under the influence of a DC voltage bias, causing a drop in surface insulation resistance (SIR) [7]. This mechanism was ruled out as the cause of low resistance for the MLCC because the morphology and distribution of material found under the capacitor was not consistent with a dendrite or a metal filament.
Printing or dispensing of solder paste is a crucial step in production of SMT printed circuit assemblies. The stencils used must be clean and free of solder paste residue to avoid misprinting or misapplying solder paste to printed circuit assemblies. Additionally, a number of factors can determine the extent to which solder paste may be left on the stencil, including the wetness and thixotropic behavior of the paste being applied, flatness of the PCBA, the positioning of the stencil with respect to the PCBA lands, the squeegee pressure, stencil aperture opening in relation to the PCBA land dimensions, and the stencil design [8]. Solder paste residue on a stencil can result in transferring paste from the bottom of the stencil onto the next board printed. Approximately 70% of surface mount technology defects are due to solder paste printing problems [8]. In the current investigation uncleaned residual solder paste on the stencil could have been deposited between the capacitor pads and become trapped under the MLCC during assembly. Alternatively, residual solder may have become dislodged from the stencil and deposited onto the region between the MLCC pads while the stencil was being removed from the board. The maximum solder joint thickness for the crystal oscillator was measured as 0.4mm as shown in Figure 11. Due to the large area and thickness of this solder joint, a large quantity of solder paste would have been applied to the stencil during assembly of the oscillator, making it possible that some solder paste residue could have dislodged off the stencil. In either case the reflow process caused the trapped solder residue to form a continuous electrical path between the solder pads. Due to the limited availability of information from the manufacturer and the board assembler, detailed information related to the stencil and how the MLCC was soldered was not available.

Conclusions and Recommendations
Based on the results of microscopy and EDS analysis, the failure was caused by solder deposited between the MLCC solder pads during the assembly process of the printed circuit board. EDS analysis results revealed the solder under the crystal oscillator to be composed of tin and copper. The composition of material found under the MLCC and the composition of solder under the crystal oscillator and the PCBA are similar.
Since our analysis revealed that stray solder was the cause of the leakage path, an effective corrective action would reduce the likelihood of stray solder being deposited on the board and going undetected prior to component placement. This should include ensuring that stencils are free of solder paste residue between printing operations by cleaning them; that unusually large apertures in the stencil are reduced in size or eliminated wherever possible; and that both printed boards and cleaned stencils are inspected if at all possible prior to the Sn next step in the process. The effectiveness of quality control measures such as cleaning and inspection should be verified using process control techniques to evaluate the robustness of the process, for example by using a design of experiments to assess the sensitivity of board cleanliness to some of the key design and process parameters.