Production support flight control computers: research capability for F/A-18 aircraft at Dryden Flight Research Center

NASA Dryden Flight Research Center (DFRC) is working with the United States Navy to complete ground testing and initiate flight testing of a modified set of F/A-18 flight control computers. The Production Support Flight Control Computers (PSFCC) can give any fleet F/A-18 airplane an in-flight, pilot-selectable research control law capability. NASA DFRC can efficiently flight test the PSFCC for the following four reasons: (1) Six F/A-18 chase aircraft are available which could be used with the PSFCC. (2) An F/A-18 processor-in-the-loop simulation exists for validation testing. (3) The expertise has been developed in programming the research processor in the PSFCC. (4) A well-defined process has been established for clearing flight control research projects for flight. This report presents a functional description of the PSFCC. Descriptions of the NASA DFRC facilities, PSFCC verification and validation process, and planned PSFCC projects are also provided.

In general, once a control law architecture is agreed upon, it is not altered until an operational deficiency warrants change.
Several This paper provides a functional description of the PSFCC. A discussion of the resources available for this type of research and of the excellent verification and validation options that researchers find at NASA DFRC is presented. In addition, potential activities or uses of the PSFCC are described. Note that use of trade names or names of manufacturers in this document does not constitute an official endorsement of such products or manufacturers, either expressed or implied, by the NASA.

FUNCTIONAL DESCRIPTION
The PSFCC design uses a Research Flight Control System (RFCS) processor in addition to the basic F/A-18 quadraplex flight control computers. The RFCS can be engaged by the pilot to exercise fullauthority control of the aircraft with research flight control laws. The basic F/A-18 flight control system is used for flight phases when the RFCS is not engaged, such as takeoff and landing. This basic flight control system also serves as the reversion mode when the RFCS control laws are disengaged. The basic F/A-18 control laws and the RFCS control laws are computed continuously during flight. Figure 1 shows how the PSFCC are integrated into the F/A-18 flight control system. The F/A-18 aircraft is controlled by a quadredundant flight control computer system. This system accepts quadredundant signals for rate gyroscopes, accelerometers, and pilot inputs. Dual input signals are used for airdata, angle of attack, and nose wheel steering (NWS). The system outputs quadredundant signals for stabilators and trailing-edge flaps. In addition, dual signals are outputted for leading-edge flaps, ailerons, and rudders. The baseline system also receives Military Specification 1553 multiplex bus data from the inertial navigation system (INS), airdata computer, and mission computers (MC).  The pilot can specify a control mode using buttons on either of the cockpit DDI. Each DDI button is programmed to send the PSFCC research software two numbers: a table number and a row number. These numbers specify which research control mode is requested. The UFC is used to program the DDI buttons with the table and row numbers.
Currently, the PSFCC research software has three flight control modes: a replication mode of the basic F/A-18 flight control system, a variable dutch roll response mode, and a mode which locks the right stabilator. The variable dutch roll response mode has three levels of lateral--directional damping: overdamped, underdamped, and unstable. A unique table and row number exists for each of these selections, providing for five research control law choices.
This portion of the PSFCC can be reprogrammed to meet future research needs.
The research software has been preprogrammed with two sets of requirements: arm requirements and engage-disengage requirements. Current aircraft parameters are evaluated against the requirements for differential stabilator, normal acceleration, yaw rate, bank angle, altitude, and Mach number. These parameters must meet the requirements to allow the system to be armed (enabled) and then engaged (activated).
The PSFCC are programmed with a     defaultsetof limits for eachresearch mode. The software contains tables of alternate limits which can be selected. These alternate limits may be selected using additional table and row numbers (by pressing another programmed button). laws are programmed in Ada and are independent of the basic control laws. Information to and from the RFCS is handled by the basic flight control system through dual port random access memory (DPRAM) to minimize communication delays and to isolate the basic system from RFCS failures. The 701E processor operates with 160-Hz subframes. It is synchronized with the RFCS using software flags. The RFCS will not start processing a frame until it receives a positive flag from the 701E processor indicating that the required data have been sent. The four F/A-18 processors are synchronized using a 10-Hz hardware pulse. The RFCS processors are synchronized with the basic F/A-I 8 processors using a 160-Hz hardware pulse.
All input-output and failure monitoring is done within the basic 701E flight control processor system. Sensor inputs, pilot inputs, and airdata parameters are transmitted to the basic flight control system through analog-to-digital (A/D) converters. These signals are then compared in the input signal management, and a selected signal is sent to the basic control laws and to the RFCS. Surface position commands from the basic F/A-18 control law and from the RFCS are sent to the output signal selection

Hardware-in-the-Loop Simulation
One essential resource to have when flight testing new aircraft systems is a hardware-in-the-loop, or in this case, a processor-in-the-loop simulation. Such simulation allows for realistic validation and failure mode testing. This simulation must be at the same location as the flight testing, so rapid examination of flight anomalies can take place. Figure 6 shows the processor-in-the-loop simulation configuration for the F/A-18 test bench. This simulation uses aircraft hardware for the PSFCC, MC's, cockpit displays, and UFC. The PSFCC are interfaced with the flight control computer console. This console exchanges information with a simulator interface device (SID) and a cockpit signalconditioning unit. The SID provides analog and digital signals used by the simulation computers. The cockpit signal-conditioning unit provides an interface with the piloted cockpit. These simulation computers contain a full six-degree-of-freedom simulation which can simulate pilot inputs and provide full data recording. A Military Specification 1553 data bus is used to interface the MC's and PSFCC and to drive the cockpit DDI. Stripchart recorder capability is available for real-time data observation.
The simulation can be driven with automated scripts, and data can be logged for posttest processing.

Experienced Personnel
During the HARV program, Ada programming and validation testing of new control laws using the  [4].

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PSFCC processor were performed. Many lessons were learned about practical issues concerning the programming of the RFCS processors. These lessons include • Portability--Ada software on the HARV program was transferred to three platforms with only system specific changes.
• Documentability--Ada is self-documenting on the code level; however, added documentation on the system level operation of Ada is necessary for coding.
• Testability--Testing requirements for the Ada software were no different than those of any other high-order language.
Reference 4 provides additional detail on these and other related issues.

Safety-of-Flight Administrative Processes
To verify that issues addressing safe flight test have been properly resolved, a process consisting of a Flight Readiness Review (FRR) and an Airworthiness and Flight Safety Review Board (AFSRB) evaluation is conducted. An FRR consists of a panel of working level personnel assigned to evaluate whether a project is safe for flight test. The project presents analysis on the safety of the proposed flight program to the FRR panel. Then, the panel determines whether the project has fulfilled the requirements for safe flight. Next, the FRR panel presents its recommendation to the AFSRB. Lastly, the AFSRB makes the final decision on flight test for a given project. Without the proper experience, the FRR panel and the AFSRB could not accurately determine if a project should go forward to flight test. Over the past 50 years, experience in this process has been acquired and refined for a broad range of aircraft and other flight vehicles. This established, provenprocessprovidesan extremelysafe and relativelyfastflight approval process.

VERIFICATION AND VALIDATION TESTING
When clearing flight control computers for flight test, verification and validation testing are necessary. Verification testing ensures that the system was fabricated correctly, and it fulfills the design requirements.
Validation testing determines if the design is suitable for the task. Validation testing uses the system under realistic conditions to determine if operational problems exist and to assess dangerous failure modes. The verification and validation testing for the initial flight test thoroughly evaluates the baseline F/A-18 flight controller and the research flight control system. In succeeding experiments, only the research flight control system will require verification and validation, thereby saving time, effort, and money for the next experiments.  Table 3 shows the testing which was conducted in each category and lists responsible organization. Note that the MDA, NASA DFRC, and USN conducted the same categories of validation testing. This overlap occurred because the NASA DFRC and USN have additional requirements which exceed the original MDA effort. In addition, the NASA DFRC and USN gathered valuable experiences during these validation tests. These experiences serve as initial training for flight test activities.

Module Level Testing
Low-level software testing was performed on the basic F/A-18 control law software by LMCS. This testing included software subroutine level testing of the 701E processor executive, BIT software, input-output signal management, and control laws.

Open-Loop Failure Testing
The MDA performed broken wire testing in which the processor-in-the-loop bench is used to disconnect various feedbacks and to determine if the computers react properly. The term open loop refers to the fact that the flight control processor is not linked to any aircraft simulation so that simulated aircraft reaction to each failure cannot be observed. Failures are individually inserted into dual redundant and quadredundant sensor and discrete signals to determine if the system reacts properly to each failure. Other failure tests include individual surface command feedback, position feedback, hydraulic system, and airdata failures.

Open-Loop Validation Testing
The MDA performed automated validation testing using a system called Flight Control Automated System Testing (FAST) on the processor-in-the-loop test setup. By inserting signal-generating software into the input plane of the baseline F/A-18 flight control computers, this automated testing validates each individual path in the control laws for functionality. The FAST is performed on the baseline F/A-18 flight control system and on the research F/A-18 replication mode.
The basic F/A-18 processors provide a great deal of flexibility in the FAST. A software routine which is patched into the basic F/A-18 processor software makes it possible to vary any software variable and to record a time history of any path in the software. As a result, thorough tests are completed. These tests use every flight control system input to every surface output and vary flight conditions for the entire envelope. Tests are conducted in the up-and-away, powered approach flight, and outer loop (automatic pilot) modes.
For the research software, FAST was performed through the DPRAM locations. Because this approach restricts the availability of internal variables to be changed, such as gains, five flight conditions were chosen. These conditions spanned the dynamic pressure envelope for the research software. The FAST is done from every flight control input to every flight control output. These tests consist of steps, ramps, and frequency sweeps. Software routines automatically perform the testing,

Closed-Loop Validation Testing
The MDA, NASA DFRC, and USN will divide the tasks for the closed-loop validation testing. The PSFCC are interfaced with a six-degree-of-freedom simulation. The configuration of which is consistent among these organizations.

Mode Transitions, Automatic Pilot Modes, and Spin Modes
In mode transition, automatic pilot, and spin mode tests, the auxiliary modes are tested for basic functionality.
Automatic pilot modes tested include heading hold, barometric altitude hold, radar altitude hold, velocity hold, automatic carrier landing system, and instrument landing system. Flap transitions tested consist of up-and-away, half-flap, and full-flap operations. The spin mode is also tested.

Piloted Tests
Pilots fly the processor-in-the-loop simulation to gain basic familiarity with the system. Safety-of-flight processes established which address the concerns for an aircraft research control system in a timely manner Once the initial flight test of the PSFCC has been completed successfully, the PSFCC facility will be useful for a variety of flight control and handling quality research experiments.
Because experiments can be designed and executed within a limited flight envelope, less work, such as analysis and testing, will be required to bring advanced concepts to flight. Advanced algorithms will be flight tested to find potential problems or payoffs associated with actual flight applications.
Flight control systems which specify airframe frequency and damping can be flight verified and used to determine handling quality ratings as a function of airframe dynamics. Alternate control sticks can be used to determine their affects on aircraft handling qualities.
In-flight excitation systems can be used for parameter identification, phase and gain or singular value calculations, and flutter or aeorsevoelasticity research.