IT'll Lawrence Berkeley Laboratory A "Winner-Take-All" IC for Determining the Crystal of Interaction in PET Detectors

We present performance measurements of a "Winner-Take All" (WTA) CMOS integrated circuit to be used with a pixel based PET detector module. Given n input voltages, it rapidly determines the input with the largest voltage, and outputs the encoded address of this input and a voltage proportional to this largest voltage. This is more desirable than a threshold approach for applications that require exactly one channel to be identified or when noise is a significant fraction of the input signal. A sixteen input prototype has been fabricated using two 1.2 !J.m processes (HP linear MOS capacitance and Orbit double-poly capacitance). ICs from both processes reliably identify (within 50 ns) the maximum channel if !:J. V (the difference between the two highest channels) is >20 mV. The key element in the WT A circuit is an array of high gain non-linear current amplifiers. There is one amplifier for each input channel, and each amplifier is composed of only two FETs. All amplifiers are supplied by a common, limited current source, so the channel with the largest input current takes all of this supply current while the other channels receive virtually none. Thus, these amplifier outputs become a set of logical bits that identify the maximum channel, which is encoded and used to select a multiplexer input. A voltage to current converter at each input channel turns this into a voltage sensitive device. This circuit uses very· little power, drawing approximately 100 !J.A at 5 V.

1. INTRODUCTION We are designing a PET (positron emission tomography) detector module to identify 511 ke V photons from positron annihilation with good spatial and temporal resolution [1,2]. This design consists of an 8 by 8 array of ~ mm square by 30 mm deep BGO scintillator crystals coupled on one end to a single photomultiplier tube and on the opposite end to a 8 by 8 array of 3 mm square silicon photodiodes. The photomultiplier tube provides an accurate timing pulse and initial energy discrimination for the 64 crystals in the module, while the silicon photodiode array identifies the crystal of interaction.
Because of the high data rates (up to 106 Hz per detector module), it is imperative that a single photodiode pixel be rapidly assigned (~100 ns) as the crystal of interaction whenever the photomultiplier tube triggers. The signal to noise ratio in the photodiode is small -typically a 700 esignal for a full 511 keV energy deposit and a 125 e-RMS noise. Compton interactions cause events with energy deposit in more than one pixel, increasing the complexity of the event topology and further reducing the signal to noise ratio. Under these conditions, a simple threshold scheme will frequently have zero or greater than one pixels above threshold, yielding ambiguous events. Therefore, we have designed a "Winner-Take-All" (WTA) circuit to rapidly identify the maximum pixel. This circuit performs a function similar to WT A circuits used in neural network applications [3,4], but uses a new design that requires significantly fewer components.

CIRCUIT DESIGN
A conceptual diagram of the WTA circuit is shown in Figure 1. Each input voltage is converted to a current proportional to this voltage and sent to the WT A circuit, whose main component is an array of n identical FETs whose gates and sources are tied together. The current proportional to the input voltage of channel i is applied to the drain of FET i, and since these FETs have common gates and sources, the FET with the highest drain current establishes a common operating point for all these transistors and determines V GS· These transistors have high output conductance, as shown schematically in the IV curve shown in Figure 2. Thus, Iiin defines VDi· and relatively small differences between the drain currents are transformed into relatively large differences between the drain voltages. The drain of each of these input FETs is connected to the gate of an output FET which, given an unlimited current supply, would produce an output current proportional to the square of the input voltage (minus an · offset) and further magnify the differences between input levels. However, all of these output FETs are supplied by a common, limited (30 !J.A) supply. Therefore, the channel with the highest input voltage (the winner) will take the entire output supply current, yielding one output with the entire supply current and the remainder with no output current. These   output currents are used as logical bits identifying the maximum channel. Note that once the voltage to current conversion has been performed, only two transistors are required for each input channel. The total current drawn is roughly 100 JlA at 5 V and is independent of the number of input channels, as 30 JlA goes to the shared current supply of the WT A and the remaining 70 JlA is drive current for the output bits. The IC fabricated is shown schematically in Figure 3, and has some additional components to facilitate use. Each voltage input has a sample and hold circuit actuated by a common logic input to allow all inputs to be strobed simultaneously. Although the individual logical output bits are provided, an address encoder is also included to provide redundant data in a more compact format. Finally, an analog multiplexer combined with an output buffer provides an output voltage that is proportional to the maximum input voltage.

CIRCUIT PERFORMANCE
Sixteen input channel prototypes were fabricated using two 1.2 Jlm processes (HJ> linear MOS capacitance and Orbit double-poly capacitance). A photograph of the resulting integrated circuit is shown in Figure 4. In order to maintain compatibility with the DC output voltage of the shaper-2 LBLr-37973 amplifier that proceeds it [5], a 2.5 V input voltage corresponds to baseline input signal, thus the dynamic range of input voltages is from 2.5 to 4.0 V. Of the 15 prototype chips produced with the HP process, 14 performed reliably. Of the chips produced with the Orbit process, the WTA portion of the circuit performed reliably on 7 of the 9 chips, but the address encoder and analog output buffer failed to perform on any of these chips. It is not known whether this failure was due to a design error or a processing error. These devices were characterized by supplying 15 of the inputs with a common voltage and the 16th input with a test voltage. The voltage difference Ll V between these two voltages is gradually reduced until the first incorrect address is detected, in<;licating that the wrong input is identified as the maximum. This minimum Ll V necessary for accurate performance is defined to be the threshold voltage for a single measurement. Figure 5 plots the mean threshold voltage (averaged over all channels on all chips) as a function of common voltage. for the two processes, as well as the "worst case" threshold voltage (i.e. the largest threshold voltage found on any channel).
For common voltages above 2.5 V, the mean voltage difference required for accurate identification is Ll V = 19 m V (with an RMS deviation of 11.6 mV) for the HP process and the "worst case" threshold voltage is typically below 60 mV. As the WT A circuit is essentially a current input circuit, this threshold of I9 m V corresponds to a 3 J..LA input current difference. For common voltages below the 2.5 V design voltage, the performance is slightly degraded but the circuit still operates reasonably well. The prototypes fabricated with the I.2 J..Lm Orbit double-poly capacitance process show similar properties, although Figure 5 shows that the threshol_d voltage increases significantly when the common voltage IS above 3.I V. Fioure 6 shows the distribution of threshold voltages taken "' over all channels of all HP process chips at all common voltages. It is reasonably well fit to a Gaussian distribution, althouoh there are some tails caused by data taken at common "' . voltages below 2.5 V. When the data correspondmg to common voltages below 2.5 V are removed (also shown in Figure 6), the distribution is well fit to a Gaussian with 11.6 mV RMS. Finally, Figure 7 shows the distribution of mean threshold voltage as a function of channel number, showing that there were no systematic threshold voltage differences between channels. The propagation delay of the chip is measured by applying a common 2.5 V sional to I5 channels and a voltage ramp "' . th going from 1.8 V to 2.8 V m 30 ns to the I6 (test) channel. The WTA output bit corresponding to the test channel is monitored on an oscilloscope, and found to change state 37 ns after its input ramp xoltage crosses the common voltage. While the propagation time is likely to depend on both the slew rate and the overdrive voltage of the test ramp, it easily meets the <IOO ns requirement for our application.

OTHERAPPLICATIONS
Although this device was developed for a PET detector module, there are other applications that could benefit from the rapid identification of the maximum input voltage. Common themes for other potential applications are: I) Multi-Element Detector Arrays. The WTA circuit is effectively a multiplexer, taking in the analog inputs of several elements and providing an analog output corresponding to the highest input, along with its digital address.
2) Low Event Multiplicity. The WTA is only capable of identifying a single channel at a time, so the detector array cannot have simultaneous signals in multiple channels that all need to be read out.
3) Poor Signal to Noise Ratio. An approach utilizing threshold discriminators would be simpler than the WT A provided that the signal was always above the threshold and the noise was always below the same threshold. However, when the signal to noise is poor, or when a single interaction causes spurious signal in other channels, the threshold discriminator approach is unreliable.

4) High Event
Rate. An approach utilizing a microprocessor to search over multiple digitized inputs (perhaps with a scanning ADC to reduce electronics channel count) would be very effective, but would have difficulty achieving events rates above I 00 khz. The WT A approach can achieve rates above I 0 Mhz.
A potential application is the readout of position sensitive photomultiplier tubes, which is presently done by determining a centroid in each of two views using a I6-18 resistor chain and current division [6]. This circuit could replace the resistor chain and current division circuit for determining the centroid [7]. Anger cameras, such as those used for SPECT or in an alternate PET design [8], could conceivably employ a circuit such as this to identify the photomultiplier tube with the largest signal in order to accurately determine the position of the gamma ray interaction. Another potential application is the readout of solid state detector arrays, such as double-sided CdZnTe micro-strip detectors used in coded-aperture telescopes for x-ray astronomy [9] .

CONCLUSIONS
We have manufactured a 16 channel prototype Winner Take All circuit that rapidly identifies (<50 ns) which input has the highest voltage, and provides both the digital address of this channel and an analog output voltage corresponding to the highest input voltage. The main portion of the circuit (the Winner Take All) is simple, requiring only two transistors per input channel. Power consumption is small -approximately 0.5 mW independent of the number of input channels. Prototype circuits have been fabricated with two 1.2 fJ.m CMOS processes and tested, and found to have reasonably good yield. The mean threshold voltage (i.e. the voltage difference required to reliably identify the input with the maximum voltage) was 19 mV with an 11.6 mV RMS deviation. The correct channel was identified in all cases when the voltage difference was >60 mV. This circuit is useful for applications that wish to economically read out detector arrays that have low event multiplicity, high event rates, and poor signal to noise ratio.