Radiation Response of Silicon on Diamond ( SOD ) Devices

Field effect msistors are fabricated on two types of Silicon-On-Diamond (SOD) structures and their radiation response is studied. The results are compared with the radiation response of simultaneously fabricated SIMOX devices. The feasibility of fabricating field effect transistors on SOD structure is demonstrated for the first time and the extreme radiation hardness of such a structure is also verified.


I. INTRODUCTION
Silicon-on-diamond1 .2(SOD) is a form of silicon-oninsulator (SOI) technology2 in which the buried insulator comprises a thin film of diamond.In addition to the generic advantages of SOI, SOD technology offers two major benefits: (1) Good thermal conducting property of diamond makes power dissipation easy and hence it is possible to develop ULSI circuits or power devices with capabilities beyond those achieved by existing technologies.(2) High chemical bond strength (50 kcal/cm3) and high carrier mobility which make diamond very insensitive to radiation, will also make SOD structure extremely radiation hardened.Although more materials work needs to be done to realize usable SOD technology, we summarize here a preliminary investigation of SOD technologies.We conducted a series of experiments to establish the extreme radiation hardness of SOD and the feasibility of fabricating SOD MOSFET devices: (1) characterization of aluminum-CVD diamond film-silicon (MIS) capacitor, (2) characterization of quick turn around (QTA) back channel MISFET's made in an experimental ZMRSOD structure1, and (3) fabrication of conventional, concentric NMOS ET'S with polysilicon gates in bond-andetchback SOD (BESOD).This paper discusses these experiments and establishes the potential of SOD as an extremely radiation hardened material.

A. MIS Capacitor:
A CVD diamond film was deposited on a 3" silicon wafer.CVD diamond3 was deposited by DC plasma reactor using 5% methane gas at 35 Torr pressure at 725" C with a power of 700W4-Thickness of diamond films ranged from 1 micron to 3.7 microns.Aluminum metal dots (4.6~10-3 cm2) were deposited on top of the diamond film.The backside of the wafer was metallized for a good substrate contact.

B. ZMRSOD Quick Turn Around QTA Back Channel MIS FET's:
Fabrication of the ZMRSOD structure used in this study is illustrated in Figure 1.Polycrystalline, intrinsic diamond films (1000 nm) were deposited on (loo), p-type silicon substrate using a well characterized, plasma CVD process.The diamond deposition was done on the wafer leaving a 0.25" rim free of diamond.One micron thick polycrystalline silicon film was deposited on this wafer covering the whole wafer, including the rim area.Using the rim area as the single crystal silicon seed, the polycrystalline silicon was crystallized into a single crystal by a zone melting recrystallization t e ~h n i q u e .~ In the ZMR process, the wafer is held at a temperature very near the melting point of silicon in an inert environment and zone melting recrystallization (ZMR) is achieved by scanning a strip heater in close proximity of the surface of the wafer.Characterization of the SOD structure was done using SEM, Raman Spectroscopy and Scanning Auger Microscopy to verify the integrity of the buried diamond film at two stages in the experiment: (1) after the deposition of the CVD diamond film on silicon wafer and (2) after completing the device fabrication.Fig. 2 shows a cross sectional scanning electron micrograph of a ZMRSOD sample after the device fabrication.
A conventional MOSFET fabrication sequence could not be applied to SOD substrates in the beginning of the work for several reasons: interaction of the CVD diamond film with various VLSI fabrication steps was not understood very well, the possibility of cross contamination of fabrication equipment was a concern, and the warp of the experimental SOD substrate would have interfered with automatic wafer handling.A quick tum around (QTA) back channel MISFET structure (Fig. 3) was devised and fabricated in a CMOS US.Government work not protected by U.S. copyright fabrication facility using a few steps to prove the feasibility of the SOD technology.The fabrication of ZMRSOD QTA back channel MISFET's, which comprised an undoped body and boron doped source and drain m-Pdysnim  During ZMR processing, plysilicon was deposited either directly on the diamond film or on top of a very thin (30 nm) baniedadhesion layer of deposited Si02.QTA back channel MISFETs were fabricated in the split which had a thin (30 nm) barriedadhesion layer of Si02.The QTA fabrication process involved use of RCA cleans, piranha clean, buffered HF dips, downstream oxygen plasma and a wet photoresist stripping solution of tetramethyl ammonium hydroxide.These steps did not have any adverse effect on either the diamond or the silicon film as judged by optical microscopic inspections and profilometer thickness measurements.
Diamond films react rapidly with oxygen above 7 b C. Hence oxidizing environments could not be used to anneal the source drain implants.A short anneal in oxygen at 9000 C in a preliminary experiment not only oxidized all the exposed diamond but caused hundreds of micron deep lateral oxidation of the diamond film under the silicon film.A low temperature anneal cycle was chosen to assure some degree of dopant activation without any risk of sample destruction by decomposition or peel off.The process steps used for fabrication of QTA back channel MISFETs are as follows: 1. Reduce Si thickness for ease of processing.
2. Form islands by photolithography and RE.
3. Define source, drain and capacitor area in photoresist.

Implant 2x1015
B+ at it30 keV and at 30 keV. 5. Clean and Sinter for 240 minutes at 455OC in N2.Electrical testing of QTA involved placing the probe needles directly on top of the source and drain regions (Fig. 3) and measuring the I-V characteristics of the back channel by using the substrate as the back gate.Good contact was obtained by lightly scrubbing the probes on the source and drain areas.

C. BESOD MOSFETs
The sequence of fabrication steps for forming a BESOD substrate can be understood from Fig. 4. Two epitaxial layers were grown on a seed silicon wafer (labelled 1 in Fig. 4): The first layer (labelled 2) was an etch stop layer with a heavy doping of boron and germanium, the second layer (labelled 3) was an undoped silicon layer of desired thickness to fabricate i 12.00 0 10.00 the field effect transistors.A 1.5 micron thick CVD diamond film, (labelled 4) was deposited on top of the undoped Si epi layer (3).On top of the diamond film (labelled 4), an approximately 10 pn thick polysilicon (labelled 5 ) was deposited and polished to obtain a smooth surface.A clean, (100) silicon wafer (labelled 6 and called a handle wafer) was bonded to the polysilicon layer.Polishing of polysilicon buffer layer was required for the intimate contact.The roughness of the diamond film made the polysilicon surface very rough and unacceptable for bonding.Wafers were bonded by placing two wafers in intimate contact at 800° C for 10 minutes in N2 ambient.
6. Contact formation by lithography and R E etch.

D. Radiation Testing:
Irradiation's were performed in an ARACOR 10 keV x-ray machine at a dose rate of 140 krad(SiO2)/min.The worst case biases used during the radiation tests are marked in the appropriate figures.Although the doses are quoted in the units of rad(SiO2) for consistency and ease of comparison with conventional SOI, the actual dose delivered to the diamond film will be less than the Si@ dose because of the lower atomic number of carbon6.Most of the seed wafer was removed by grinding the backside.EPW (ethylenediamine-pyatechol-water) was used to remove the remaining handle wafer up to the etch stop layer.Another etchant [l part HF (49%), 3 part HNO3 (70%), and 8 parts CH3COOHI was used to remove the etch stop layer.The residual layer at the end of etch stop layer was removed by a proprietary non-selective etch.

RESULTS AND DISCUSSION:
A number of discrete MOSFET's were fabricated in the BESOD silicon film (labelled 3 in Fig. 4).The device structure was concentric in geometry and consisted of a drain area with diameter of 40 pm separated from the source by the gate, having an inside diameter of 40 pm and an outside diameter of 48 pm.For comparison, a few of the SIMOX wafers were concurrently subjected to the same type of processing steps.The following fabrication process was used for BESOD MOSFET's: 1. Mesa formation by photolithography, reactive ion etch and resist removal.

A. MIS Capacitor:
The C-V Characteristics of an MIS diamond film capacitor as a function of the total dose are shown in Figure 5.
Considering that the thickness of the diamond dielectric in this structure was 1.5 pn, a shift of -30 V after a total dose of 40 Mrad(SiO2) is very small.The threshold voltage shift in the case of a buried silicon dioxide of the same thickness will be extremely high7.The radiation induced flat band shifts observed in this work are larger than those observed in a previous publication8 which examined very thick diamond films.Although we do not have a satisfactory explanation for this apparent discrepancy, it could simply be related to different thicknesses of diamond films, different applied electric fields, or to an unknown variation in the quality of the does not allow any significant charge trapping.In the previous work8, the radiation hardness of diamond films has been speculatively related to the high mobility of charge carriers in diamond.Unfortunately, the previous experiments and those discussed in this paper were not designed to identify the origin of the radiation hardness in diamond films.A separate study of the physics and chemistry of the radiation damage in diamond films is required.Interface states between silicon and diamond film also need to be characterized.

7
The dielectric constant of the diamond films, estimated from the C-V measurements, was found to be It is higher than that of natural diamond and might indicate the presence of non-diamond components in the thin film.A careful analysis of the films with very high resistivity is needed to u " d the dielectric properties.The intrinsic diamond film resistivity was also studied as a function of the electric field using MIS structures formed by 0.0046 an2 thin film, aluminum dots deposited through a shadow mask directly on a CVD diamond film and also on the diamond film obtained after ZMR processing by etching off the top silicon film.The conductivity of diamond (Fig. 6).which was symmetric in applied voltage, was very uniform over the sample area of over 10 cm2 indicating that the conductivity was not a result of localized defects.The defects or the structure and composition that made the film less insulating had a uniform distribution over the diamond film.
The through current density increased roughly two orders of magnitude after the ZMR processing which involves heating the wafer to temperatures near the melting point of Si.
Decomposition of some of the diamond could occur at such high temperatures.In the case of ZMRSOD with a 30 nm Si02 barrier layer under the Si Tim, the leakage current through the buried dielectric was low enough (nA range) to allow observation of good ZMRSOD back channel MISFET characteristics.On the other hand, the buried diamond insulator in BESOD samples was electrically very leaky and h e m BESOD back channel MISFETs could not be tested.

B. ZMRSOD Back Channel MISFETs
ZMRSOD quick turnaround back channel MISFET's exhibited good I-V characteristics with threshold voltages in the range of 4 to 11 volts, subthreshold slopes in the range of 1200 to 2000 mV/dec and maximum low field p-carrier mobility was 40 cm2 N-s.The low threshold voltage is due to the lack of intentional doping of the channel (body) region of the MISFET.The low mobility, which did not vary significantly after irradiation, indicates the presence of interface roughness, impurities, and defects in the experimental ZMRSOD substrates which is not surprising.The subthreshold swing indicates the density of interface states to be of the order of lo1 l/eV-cm2.The leakage current in the off state is high (nA) because the annealing of the source and drain implant at the low temperature did not form good junctions.
Although deleterious and in need of improvement, small back gate leakage (100 PA at VB = 5 V) did not change upon irradiation and did not interfere with the measurement of the MISFET characteristics.NMOSFETs with nearly ideal in the Same SIMOX material using the conventional CMOS the threshold voltage fabrication process.The plasma enhanced CVD process, for is lager than the -lo Fig. 7 for a ZMRSOD MISFET.The radiation induced gate oxide and does not threshold voltage shifts for SIMOX and SOD are compared in Fig. 9 which very clearly indicates the superior radiation resistance of SOD.The most striking feature of the SOD threshold voltage shifts is the reversal in reversal is not clear from the present investigation, we buried SOD dielectric.The buried dielectric in Figs.7 and 9 dewsition into SOD of device a s 1 fabrication gate oxides sequence. of better Low temperature speculate that it is caused by mapping Of negative charge in the than that of Oxide saturate at higher doses.The responsible for the poor (1970 mV/dec) subthreshold swing of diamond film or the oxide-diamond interface probably traps The subthreshold swing is swings have been fabricated Seen above 278 krad(Si02)' the Origin Of this though not optimized as a gate oxide process, was selected because it was available and could be implemented contained a thin (30 nm) layer of Si02 k w e e n the dimmd the oxides used in this work is now pssible9.on the and the si film.Only positive are in the hand, we believe that the quality of the material is mainly The silicondiamond interface was created during the deposition of diamond on silicon at an elevated temperature.The density of interfae states o r this interface was not determined because of the high leakage through the diamond film.The back gate (substrate) did not have much of a control in the device performance due to the conductivity of the diamond.This lack of electrical isolation of the Si film from the back side Si substrate might also have contributed to the poor subthreshold swing.As discussed in the ZMRSOD section and also in Ref.
8. a thin layer of Si@ between the BESOD Si film and the diamond film might have helped in improving the I-V curve by improving the diamond-Si film interface8.But the interfacial Si02 layer was avoided in an attempt to deposit high quality, insulating diamond films directly on Si.
This experiment demonstrated for the first ,time that it is possible to fabricate BESOD FET's.The buried dielectric radiation hardness, which is inherent to the diamond film, is not experimentally proven for the BESOD case.We hope to accomplish this by first resolving the fabrication issues such as obtaining smooth, electrically insulating diamond films and controlling the quality of Si film and the diamond-Si film interface by using different interfacial layers.

IV. CONCLUSION
Silicon on diamond technology is experimentally evaluated as an alternate radiation hardened device technology.The extreme radiation hardness of CVD diamond films is established by using a MIS capacitor structure and the ZMRSOD quick turn around (QTA) back channel MISFET structure.The feasibility of fabricating BESOD FET's has been demonstrated for the first time in this work.But the radiation hardness of the buried diamond in the BESOD structure could not be proven due to the excessive electrical conductivity of the buried diamond film.A number of fabrication issues were encountered in this work.However, their detailed discussion is beyond the scope of this paper.It must be acknowledged that the sensitivity of diamond to high temperature processing especially in oxidizing environments does make fabrication of ICs in the generic SOD structure very difficult.But we believe that SOD devices can be realized using modified SOD structures, modified device structures, novel fabrication sequences, and high quality deposited dielectrics.The work described here needs to be continued to optimize diamond films from the point of view of SOD device technology, development of viable SOD substrate and device fabrication technologies, and verification of the tolerance of SOD to radiation as well as high temperatures.

V. ACKNOWLEDGMENTS
Thanks are due to Mr. Mike Batty and D. P. Vu of Kopin Corporation for the Z M R work, the Digital Integrated Circuits Group at Lincoln Laboratory for device fabrication, and Dr. Walter Shedd for the use of Phillips Laboratory radiation Facilities.

Figure 2 .
Figure 2. SEM cross section of a ZMRSOD sample after device fabrication.regions, provided better understanding of the various fabrication issues and allowed study electrical properties of the SOD material.

2 .
RCA clean, 80 nm PECVD oxide deposition, and annealing at 800' C in N2 for 30 min.3. Deposition of in-situ doped, n-type polysilicon and gate electrode formation by photolithography, reactive ion etch and resist removal.4. Definition and ion implantation of NMOS source/drain areas.

Figure 5 .
Figure 5. C-V characteristics of an MIS diamond capacitor as a function of total dose, with wafer grounded and aluminum contact held at +5 V during irradiation.

Figure 6 .
Figure 6.Leakage current characteristics of a CVD diamond film on silicon.

Figure 7 .Figure 8 .Figure 9 .
Figure 7. Subthreshold characteristics of a ZMRSOD QTA back channel MISFET as a function of the total x-ray dose.Subthreshold characteristics of a ZMRSOD back channel MISFET are shown in Figure 7 as a function of the x-ray dose.'Ihe source and drain were grounded during irradiation and

I 2 0 2 4 vc ( 9 Figure 10 .Figure 11 .
Figure 10.Subthreshold characteristics of a front channel BESOD NMOSFET as a function of the total x-ray dose.