Bottom-up approach for carbon nanotube interconnects

We report a bottom-up approach to integrate multiwalled carbon nanotubes ~MWNTs! into multilevel interconnects in silicon integrated-circuit manufacturing. MWNTs are grown vertically from patterned catalyst spots using plasma-enhanced chemical vapor deposition. We demonstrate the capability to grow aligned structures ranging from a single tube to forest-like arrays at desired locations. SiO2 is deposited to encapsulate each nanotube and the substrate, followed by a mechanical polishing process for planarization. MWNTs retain their integrity and demonstrate electrical properties consistent with their original structure. © 2003 American Institute of Physics. @DOI: 10.1063/1.1566791 #

and 9.The extraordinary electrical, mechanical, and thermal properties of CNTs may provide near-term solutions for problems in interconnects, chip cooling, etc. in silicon IC technology.For example, Wei et al. 10 showed that the current carrying capacity of multiwalled CNTs ͑MWNTs͒ did not degrade after 350 h at current densities of 10 10 A/cm 2 at 250 °C.The thermal conductivity of CNTs 11,12 is about 1700-3000 W/m K.The mechanical properties of CNTs are also superior to those of traditional materials used in the IC industry.
Kreupl et al. 13 recently deposited MWNTs inside 400 nm vias and 5ϫ5 m 2 contact holes ͑1.25 m depth͒.Although their estimated resistance per nanotube of 600 k⍀ was high, this value will certainly decrease as CNT growth matures and the quality of the CNT-metal contacts improves.But this approach does not offer a viable solution to interconnect problems.It is well known that CNTs, as deposited on substrates and inside trenches, appear as ''noodles.''The anticipated ballistic transport is unlikely to happen in entangled nanotubes.Although the reported fill factor is low and can be improved in the future, planarization by chemical mechanical polishing ͑CMP͒ is likely to unravel the noodles.This approach simply replaces Cu or Al with CNTs and relies on the traditional etch-deposition-planarization path; thus all the problems of high aspect ratio etching of vias and holes remain.Seeding the bottom of a deep trench with the catalyst for CNT growth may also become an issue.We offer an alternative solution in which MWNTs are first grown at prespecified locations, then gap filled with SiO 2 , and finally planarized.This bottom-up approach eliminates the etching step, already provides an aspect ratio of 20 or more uniform diameter interconnects, eliminates void-related problems since the SiO 2 is gap filled rather than CNTs and provides a SiO 2 -CNT structure that is smooth, mechanically stable, and withstands the aggressiveness of CMP.
Figure 1 shows a schematic of our process sequence.A Si ͑100͒ wafer covered with 500 nm thermal oxide and 200 nm Cr ͑or Ta͒ lines is used to deposit 20 nm thick Ni as a catalyst.Ion beam sputtering is used to deposit Ni on patterned spots for local wiring or contact hole applications; for global wiring, Ni can be deposited as a 20 nm thick micron-a͒ Electronic mail: jli@mail.arc.nasa.govb͒ Also at: ELORET Corporation.scale film.Then plasma enhanced chemical vapor deposition ͑PECVD͒ is used to grow a low density MWNT array by an inductively coupled plasma process or dc plasma-assisted hot filament CVD as reported previously. 14 -16Each CNT is vertically aligned and freestanding on the surface ͑see Fig. 2͒.Such CNT structures are not possible by thermal CVD but are produced by PECVD due to the electric field normal to the substrate. 14Next, the free space between the individual CNTs is filled with SiO 2 by CVD using tetraethylorthosilicate ͑TEOS͒. 16This is followed by CMP to produce a CNT array embedded in SiO 2 with only the ends exposed over the planarized solid surface. 16The top metal line may also be deposited although it is omitted here.
Figure 2 shows scanning electron microscopy ͑SEM͒ and transmission electron microscopy ͑TEM͒ images of some CNT arrays at various stages of processing.Wellseparated, vertically aligned MWNTs are grown on ϳ100 nm diam catalyst spots ͓Fig.2͑a͔͒ and 2 m spots ͓Fig.2͑b͔͒ defined by e-beam and UV lithography, respectively.The 2 m spots each have approximately 10 nanotubes.The nanotubes have an aspect ratio of up to 100:1 and lengths varying from 2 to 10 m ͑depending on the growth time and condi-tions͒ and diameters of between 30 to 200 nm ͑depending on the diameter of the patterned spot and the catalyst thickness͒.
Figure 2͑c͒ shows MWNTs on a catalyst film deposited at alignment markers over 10 m in size.In all cases, we have successfully grown uniform MWNT arrays with uniform diameters along the axis from the base to the top ͓Figs.2͑g͒ and 2͑h͔͒.Attachment of the nanotubes to the substrate is very strong and they cannot be removed easily.
SiO 2 deposition is found to be conformal around each nanotube as well as on the substrate.When the SiO 2 film grows thicker, it starts to break down to about 2-3 m size grains.For catalyst spots smaller than 2 m, we found that the CNTs are normally embedded within a single SiO 2 grain whereas multiple grains form for larger spot sizes ͓Figs.2͑d͒-2͑f͔͒.The Cr surface is also covered with a uniform SiO 2 film about 3 m in thickness ͑not shown͒.There are some voids ͑р100 nm in size͒ inside the SiO 2 film as a result of the grain boundaries.This can be avoided for catalyst spot sizes less than 2 m.Although not optimized, TEOS CVD has shown the formation of a conformal SiO 2 layer around CNTs and good gap-filling properties.The CMP process removes the excess SiO 2 and breaks the CNTs resulting in a planarized SiO 2 surface with only the very ends of the CNTs exposed.As shown in Fig. 2͑i͒, the CNTs extend about 30-50 nm above the SiO 2 surface, likely due to their better mechanical resilience.Bright contrast indicates conformal SiO 2 wrapping around each individual CNT even in the portion that protrudes.
The planarized SiO 2 -CNT structure without the top metal line is amenable to current-voltage (I -V) measurements using atomic force microscopy ͑AFM͒ modified with a current sensing AFM ͑CSAFM͒ module.This technique can be used to measure electrical properties of individual CNTs.The Si 3 N 4 cantilever was coated with a Pt film so that voltage bias can be applied.Figure 3 shows images of the topography, deflection, and current of an embedded CNT sample ͓grown on a macro-sized continuous catalyst film like in Fig. 2͑i͔͒ and corresponding profiles along the line on the surface as highlighted.The topography clearly indicates that CNTs protrude out of the SiO 2 matrix, consistent with the SEM image in Fig. 2͑i͒.The black spots in Fig. 3͑c͒ correlate well with the protruding CNTs, indicating that CNTs have higher conductance than the SiO 2 matrix.Clearly, the CNTs are well separated in the SiO 2 matrix.
Corresponding to the CSAFM image in Fig. 3͑c͒, the AFM tip can be easily positioned over different conducting spots to generate I -V curves of individual CNTs quickly.Figure 3͑d͒ shows typical I -V curves of a single MWNT and a compact bundle (ϳ250ϫ500 nm 2 ) in the embedded array.The I -V curve of the single MWNT is a straight line within the instrumental limits of Ϯ10 nA.The resistance of the single MWNT is about 300 k⍀ but that of the bundle is much lower than the 2 k⍀ instrumental limit.The I -V curve of the insulating SiO 2 shows a flat line at zero with 1 pA root mean square ͑rms͒ noise.Further measurements using a fourprobe station linked to a semiconductor parameter analyzer were carried out to inspect the bundles in the Ϯ5.0 V range.As shown in the inset of Fig. 3͑d͒, a perfect linear curve is observed that has resistance of 5.2 k⍀, corresponding to about 60 MWNTs in parallel contact with the 25 m diam probe, consistent with the CNT density seen in Fig. 3͑c͒.In these experiments, repeatedly applying ϳ1ϫ10 6 A/cm 2 cur- rent density for many hours did not show any damage according to the I -V measurements.It was already reported 10 there was no degradation even at 10 10 A/cm 2 with only loose thermal contacts.So, it is expected that CNTs embedded in a SiO 2 matrix would withstand current densities far higher than that desired by the ITRS. 1 Ballistic transport in MWNTs with quantized conductance corresponds to resistance of 12.9 k⍀. 8 The resistance measured here of a single MWNT is more than an order of magnitude higher than the theoretical value.Nevertheless, the use of a compact bundle or increasing the number of MWNTs in contact may already be sufficient for global wiring.There are several reasons for the observed resistance and possible ways to reduce it.First, the contacts to nanotubes to date are not perfect.Typically, 13 metal contact has always been to the sidewall of CNTs.In the case of MWNTs, contact then is only to the outermost shell.In our approach, contact is made to all the shells which is favorable for interconnect applications.Theoretical studies 17,18 show that the length of contact between the metal and the nanotube is critical for low resistance.The conductance drops dramatically when the contact length is less than 10 nm.For the point contact geometry of CSAFM used here, this may be a valid issue and along with the AFM tip/CNT contact may contribute to the observed resistance.In practice, a catalyst metal such as Fe, Co, or Ni may be deposited on top of the MWNTs before deposition of the top metal line.Thermal annealing in the presence of the transition metal can improve the electrical contact between CNTs and metal lines. 19On the bottom side, MWNTs are grown directly from the substrate and show strong attachment to the metal film on the substrate, so good electrical contact may be possible.
Finally, the quality of the material itself contributes to the resistance observed.It is known 14 -16 that most plasmagrown structures are somewhat defective, and are characterized by periodic bamboo-like or ice cream cone-like closed shells along the axis, as confirmed by TEM images.Whereas an ideal MWNT will have all walls parallel to the center axis (ϭ0), most plasma-grown structures exhibit small values and hence they are sometimes referred to as multiwalled carbon nanofibers. 14In any case, the electrons have to cross the graphitic layers in such structures in order to be transported from one end to the other.This gives much larger resistance, similar to what one would get perpendicular to the basal plane of graphite.True ballistic behavior is possible with ideal MWNTs.We are currently investigating postgrowth annealing as well as higher temperature growth to reduce the resistance.The conductance may also be increased by introducing intercalation species such as I or Br to improve electron transport across graphitic layers. 20n summary, we have demonstrated a material and processing solution to integrate carbon nanotubes into multilevel interconnects to meet future silicon IC needs.The process sequence, which involves plasma deposition of CNTs, dielectric gap filling, planarization, annealing, etc., is compatible with current IC manufacturing practice.
Work by the authors at ELORET was supported by a NASA contract.FIG. 3. Images of the ͑a͒ topography, ͑b͒ deflection, and ͑c͒ current sensing ͑at Ϫ5 mV͒ of a 5ϫ5 m 2 planarized CNT array embedded in a SiO 2 matrix with profiles along the line marked.The scale bars for the profiles are as noted except for deflection ͑arbitrary͒.͑d͒ I -V curve of a single CNT ͑open circles͒ and a 250ϫ500 nm 2 compact bundle ͑closed circles͒ in the embedded array, both measured with CSAFM.Inset: I -V curve of a parallel contacted CNT array measured with a four-probe station linked to a semiconductor analyzer.